📄 fw.lst
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ARM macroassembler Page:1
1 00000000 ;******************************************************************************
2 00000000 ;*
3 00000000 ;* System On Chip(SOC)
4 00000000 ;*
5 00000000 ;* Copyright (c) 2002 Software Center, Samsung Electronics, Inc.
6 00000000 ;* Copyright (c) 2002 Mobile Solution Project Team, Samsung Electronics, Inc.
7 00000000 ;* All rights reserved.
8 00000000 ;*
9 00000000 ;* This software is the confidential and proprietary information of Samsung
10 00000000 ;* Electronics, Inc("Confidential Information"). You Shall not disclose such
11 00000000 ;* Confidential Information and shall use it only in accordance with the terms
12 00000000 ;* of the license agreement you entered into Samsung.
13 00000000 ;*
14 00000000 ;*-----------------------------------------------------------------------------
15 00000000 ;*
16 00000000 ;* S3C2410 BSP (WinCE.NET)
17 00000000 ;*
18 00000000 ;* fw.s : BSP Startup Code(Entry Point)
19 00000000 ;*
20 00000000 ;* @author zartoven@samsung.com (SOC, SWC, SAMSUNG Electronics)
21 00000000 ;*
22 00000000 ;* @date 2002/04/04
23 00000000 ;*
24 00000000 ;* Log:
25 00000000 ;* 2002/04/04 Start
26 00000000 ;* 2002/05/24 Add Power Management Function(zartto)
27 00000000 ;* 2002/09/13 Porting to CE.NET(hmseo)
28 00000000 ;*
29 00000000 ;******************************************************************************
30 00000000
31 00000000
38 00000000 OPT 1
39 00000000 OPT 128
40 00000000
41 00000000 ;---------------------------------------------------------------------------
42 00000000 ; 4 LED light function
43 00000000 ; The LEDs are located below AMD Flash ROM
44 00000000
45 00000000 MACRO
46 00000000 LED_ON $data
47 00000000 LDR r10, =0x56000054
48 00000000 LDR r11, =$data
49 00000000 MOV r11, r11, lsl #4
50 00000000 STR r11, [r10]
51 00000000 MEND
52 00000000 ;---------------------------------------------------------------------------
53 00000000 ;---------------------------------------------------------------------------
54 00000000 ; 4 LED light function
55 00000000 ; The LEDs are located below AMD Flash ROM
56 00000000
57 00000000 MACRO
58 00000000 VLED_ON $data
59 00000000 LDR r10, =0xB1600054
60 00000000 LDR r11, =$data
61 00000000 MOV r11, r11, lsl #4
62 00000000 STR r11, [r10]
63 00000000 MEND
64 00000000 ;---------------------------------------------------------------------------
65 00000000
66 00000000 IMPORT KernelStart
67 00000000
68 00000000 IMPORT TLBClear
69 00000000 IMPORT FlushICache
70 00000000 IMPORT FlushDCache
71 00000000
72 00000000 FCLK EQU (203)
73 00000000 PLLVAL EQU (((0xa1 << 12) + (0x3 << 4) + 0x1))
74 00000000 ;PLLVAL EQU ((((FCLK - 8) << 12) + (0x4 << 4) + 0x1))
75 00000000 ;PLLVAL EQU ((((0x5f) << 12) + (0x4 << 4) + 0x0))
76 00000000
77 00000000 R1_iA EQU (1 << 31)
78 00000000 R1_nF EQU (1 << 30)
79 00000000
80 00000000 ;SLEEPDATA_BASE_VIRTUAL EQU 0xAC058000 ; keep in sync w/ config.bib
81 00000000 ;SLEEPDATA_BASE_PHYSICAL EQU 0x30058000
82 00000000 SLEEPDATA_BASE_VIRTUAL EQU 0xA0008000 ; keep in sync w/ config.bib
83 00000000 SLEEPDATA_BASE_PHYSICAL EQU 0x30008000
84 00000000
85 00000000 WORD_SIZE EQU (4)
86 00000000
87 00000000 SleepState_Data_Start EQU (0)
88 00000000
89 00000000 SleepState_WakeAddr EQU (SleepState_Data_Start )
90 00000000 SleepState_MMUCTL EQU (SleepState_WakeAddr + WORD_SIZE )
91 00000000 SleepState_MMUTTB EQU (SleepState_MMUCTL + WORD_SIZE )
92 00000000 SleepState_MMUDOMAIN EQU (SleepState_MMUTTB + WORD_SIZE )
93 00000000 SleepState_SVC_SP EQU (SleepState_MMUDOMAIN + WORD_SIZE )
94 00000000 SleepState_SVC_SPSR EQU (SleepState_SVC_SP + WORD_SIZE )
95 00000000 SleepState_FIQ_SPSR EQU (SleepState_SVC_SPSR + WORD_SIZE )
96 00000000 SleepState_FIQ_R8 EQU (SleepState_FIQ_SPSR + WORD_SIZE )
97 00000000 SleepState_FIQ_R9 EQU (SleepState_FIQ_R8 + WORD_SIZE )
98 00000000 SleepState_FIQ_R10 EQU (SleepState_FIQ_R9 + WORD_SIZE )
99 00000000 SleepState_FIQ_R11 EQU (SleepState_FIQ_R10 + WORD_SIZE )
100 00000000 SleepState_FIQ_R12 EQU (SleepState_FIQ_R11 + WORD_SIZE )
101 00000000 SleepState_FIQ_SP EQU (SleepState_FIQ_R12 + WORD_SIZE )
102 00000000 SleepState_FIQ_LR EQU (SleepState_FIQ_SP + WORD_SIZE )
103 00000000 SleepState_ABT_SPSR EQU (SleepState_FIQ_LR + WORD_SIZE )
104 00000000 SleepState_ABT_SP EQU (SleepState_ABT_SPSR + WORD_SIZE )
105 00000000 SleepState_ABT_LR EQU (SleepState_ABT_SP + WORD_SIZE )
106 00000000 SleepState_IRQ_SPSR EQU (SleepState_ABT_LR + WORD_SIZE )
107 00000000 SleepState_IRQ_SP EQU (SleepState_IRQ_SPSR + WORD_SIZE )
108 00000000 SleepState_IRQ_LR EQU (SleepState_IRQ_SP + WORD_SIZE )
109 00000000 SleepState_UND_SPSR EQU (SleepState_IRQ_LR + WORD_SIZE )
110 00000000 SleepState_UND_SP EQU (SleepState_UND_SPSR + WORD_SIZE )
111 00000000 SleepState_UND_LR EQU (SleepState_UND_SP + WORD_SIZE )
112 00000000 SleepState_SYS_SP EQU (SleepState_UND_LR + WORD_SIZE )
113 00000000 SleepState_SYS_LR EQU (SleepState_SYS_SP + WORD_SIZE )
114 00000000
115 00000000 SleepState_Data_End EQU (SleepState_SYS_LR + WORD_SIZE )
116 00000000
117 00000000 SLEEPDATA_SIZE EQU (SleepState_Data_End - SleepState_Data_Start) / 4
118 00000000
119 00000000
120 00000000 MMU_CTL_MASK EQU 0x3FFF0000
121 00000000 MMU_TTB_MASK EQU 0x00003FFF
122 00000000 MMU_ID_MASK EQU 0xFFFFFFF0
123 00000000
124 00000000 Mode_USR EQU 0x10
125 00000000 Mode_FIQ EQU 0x11
126 00000000 Mode_IRQ EQU 0x12
127 00000000 Mode_SVC EQU 0x13
128 00000000 Mode_ABT EQU 0x17
129 00000000 Mode_UND EQU 0x1B
130 00000000 Mode_SYS EQU 0x1F
131 00000000
132 00000000 I_Bit EQU 0x80
133 00000000 F_Bit EQU 0x40
134 00000000
135 00000000 BIT_SELFREFRESH EQU (1<<22)
136 00000000
137 00000000 ;**
138 00000000 ; * StartUp - Image EntryPoint
139 00000000 ; *
140 00000000 ; * @return .
141 00000000 ; * @param .
142 00000000 ; *
143 00000000
144 00000000 STARTUPTEXT
145 00000000 LEAF_ENTRY StartUp
146 00000000 ea000003 b ResetHandler
147 00000004 e5801000 str r1, [r0] ; Enable SDRAM self-refresh
148 00000008 e5823000 str r3, [r2] ; MISCCR Setting
149 0000000c e5845000 str r5, [r4] ; Power Off !!
150 00000010 eafffffe b .
151 00000014 ResetHandler
152 00000014
153 00000014 ; LED_ON 0xa
154 00000014
155 00000014 eb000000 bl TLBClear
156 00000018 eb000000 bl FlushICache
157 0000001c eb000000 bl FlushDCache
158 00000020 e1a00000 nop
159 00000024 e1a00000 nop
160 00000028 e1a00000 nop
161 0000002c
162 0000002c e59f01b0 ldr r0, = GPFCON
163 00000030 e59f11b0 ldr r1, = 0x55aa
164 00000034 e5801000 str r1, [r0]
165 00000038
166 00000038 e3a00453 ldr r0, = WTCON ; watch dog disable
167 0000003c e3a01000 ldr r1, = 0x0
168 00000040 e5801000 str r1, [r0]
169 00000044
170 00000044 e59f01a0 ldr r0, = INTMSK
171 00000048 e3e01000 ldr r1, = 0xffffffff ; all interrupt disable
172 0000004c e5801000 str r1, [r0]
173 00000050
174 00000050 e59f0198 ldr r0, = INTSUBMSK
175 00000054 e59f1198 ldr r1, = 0x7ff ;all sub interrupt disable
176 00000058 e5801000 str r1, [r0]
177 0000005c
178 0000005c e59f0194 ldr r0, = INTMOD
179 00000060 e3a01000 mov r1, #0x0 ; set all interrupt as IRQ
180 00000064 e5801000 str r1, [r0]
181 00000068
182 00000068 e59f018c ldr r0, = CLKDIVN
183 0000006c e3a01003 ldr r1, = 0x3 ; 0x0 = 1:1:1 , 0x1 = 1:1:2
184 00000070 ; 0x2 = 1:2:2 , 0x3 = 1:2:4, 0x8 = 1:4:4
185 00000070 e5801000 str r1, [r0]
186 00000074
187 00000074 e2111002 ands r1, r1, #0x2 ; Make AsyncBusMode
188 00000078 0a000002 beq %F1
189 0000007c
190 0000007c ee110f10 mrc p15, 0, r0, c1, c0, 0
191 00000080 e3800103 orr r0, r0, #R1_nF:OR:R1_iA
192 00000084 ee010f10 mcr p15, 0, r0, c1, c0, 0
193 00000088 1
194 00000088 e3a00313 ldr r0, = LOCKTIME ; To reduce PLL lock time, adjust the LOCKTIME register.
195 0000008c e3e014ff ldr r1, = 0xffffff
196 00000090 e5801000 str r1, [r0]
197 00000094
198 00000094 e59f0164 ldr r0, = MPLLCON ; Configure MPLL
199 00000098 ; Fin=12MHz, Fout=50MHz
200 00000098 e59f1164 ldr r1, = PLLVAL
201 0000009c e5801000 str r1, [r0]
202 000000a0
203 000000a0 e59f0160 ldr r0, = UPLLCON ; Fin=12MHz, Fout=48MHz
204 000000a4 e59f1160 ldr r1, = ((0x48 << 12) + (0x3 << 4) + 0x2)
205 000000a8 e5801000 str r1, [r0]
206 000000ac
207 000000ac e3a00a02 mov r0, #0x2000
208 000000b0 1
209 000000b0 e2500001 subs r0, r0, #1
210 000000b4 1afffffd bne %B1
211 000000b8
212 000000b8 ; :::::::::::::::::::::::::::::::::::::::::::::
213 000000b8 ; Add for Power Management
214 000000b8 ; - - - - - - - - - - - - - - - - - - - - - - -
215 000000b8 e59f1150 ldr r1, =GSTATUS2 ; Determine Booting Mode
216 000000bc e591a000 ldr r10, [r1]
217 000000c0 e31a0002 tst r10, #0x2
218 000000c4 0a000000 beq %F2 ; if not wakeup from PowerOffmode
219 000000c8 ; goto Watchdog reset test.
220 000000c8 ea000011 b %F3 ; if wakeup from PowerOff mode
221 000000cc ; goto Power-up code.
222 000000cc ; Watchdog reset
223 000000cc 2
224 000000cc e31a0004 tst r10, #0x4 ; In case of the wake-up from Watchdog reset,
225 000000d0 ; go to SDRAM start address(0x3004_0000)
226 000000d0 0a000013 beq %F4 ; If not wakeup from Watchdog reset,
227 000000d4 ; goto Normal Mode.
228 000000d4
229 000000d4 e3a00004 mov r0, #4
230 000000d8 e5810000 str r0, [r1] ; Clear the GSTATUS2. Because same code is located in
memory address.
231 000000dc
232 000000dc ; Set memory control registers
233 000000dc e28f0d05 add r0, pc, #SMRDATA - (. + 8)
234 000000e0 e3a01312 ldr r1, = BWSCON ; BWSCON Address
235 000000e4 e2802034 add r2, r0, #52 ; End address of SMRDATA
236 000000e8 loop0
237 000000e8 e4903004 ldr r3, [r0], #4
238 000000ec e4813004 str r3, [r1], #4
239 000000f0 e1520000 cmp r2, r0
240 000000f4 1afffffb bne loop0
241 000000f8
242 000000f8 e3a01c01 mov r1, #256
243 000000fc loop1
244 000000fc e2511001 subs r1, r1, #1 ; wait until the SelfRefresh is released.
245 00000100 1afffffd bne loop1
246 00000104
247 00000104 e3a02a41 ldr r2, =0x41000 ; offset into the RAM
248 00000108 e2822203 add r2, r2, #0x30000000 ; add physical base
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