📄 cache.lst
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ARM macroassembler Page:1
1 00000000 ;++
2 00000000 ; Copyright (c) 1997-2000 Microsoft Corporation. All rights reserved.
3 00000000 ;
4 00000000 ; Module Name:
5 00000000 ; cache.s
6 00000000 ;
7 00000000 ; Abstract:
8 00000000 ; This module implements the code necessary to manage the CPU caches on the
9 00000000 ; ARM processor.
10 00000000 ;--
13 00000000 OPT 1 ; reenable listing
14 00000000 OPT 128 ; disable listing of macro expansions
15 00000000
16 00000000
17 00000000
18 00000000 TEXTAREA
19 00000000
20 00000000
21 00000000 LEAF_ENTRY TLBClear
22 00000000 ;++
23 00000000 ; Routine Description:
24 00000000 ; Flush and invalidate the Instruction & Data TLBs for the ARM920
25 00000000 ;
26 00000000 ; Syntax:
27 00000000 ; void TLBClear(void);
28 00000000 ;
29 00000000 ; Arguments:
30 00000000 ; -- none --
31 00000000 ;
32 00000000 ; Return Value:
33 00000000 ; -- none --
34 00000000 ;--
35 00000000 ee080f15 mcr p15, 0, r0, c8, c5, 0 ; Invalidate I tlb
36 00000004 ee080f16 mcr p15, 0, r0, c8, c6, 0 ; Invalidate D tlb
37 00000008
38 00000008 IF Thumbing
40 00000008 ELSE
41 00000008 e1a0f00e mov pc, lr ; return
42 0000000c ENDIF
43 0000000c
44 0000000c LEAF_ENTRY FlushICache
45 0000000c ;++
46 0000000c ; Routine Description:
47 0000000c ; Flush and invalidate the Instruction Cache for ARM920
48 0000000c ;
49 0000000c ; Syntax:
50 0000000c ; void FlushICache(void);
51 0000000c ;
52 0000000c ; Arguments:
53 0000000c ; -- none --
54 0000000c ;
55 0000000c ; Return Value:
56 0000000c ; -- none --
57 0000000c ;--
58 0000000c
59 0000000c ee070f15 mcr p15, 0, r0, c7, c5, 0 ; flush the icache
60 00000010
61 00000010 IF Thumbing
63 00000010 ELSE
64 00000010 e1a0f00e mov pc, lr ; return
65 00000014 ENDIF
66 00000014
67 00000014 LEAF_ENTRY FlushDCache
68 00000014
69 00000014 ;++
70 00000014 ; Routine Description:
71 00000014 ; Clean and invalidate the Data Cache
72 00000014 ;
73 00000014 ; The following code is called to flush the dcache on the ARM920. It does
74 00000014 ; a clean and invalidate on each cache line using the index and segment.
75 00000014 ;
76 00000014 ; This routine assumes a 16K cache with 64 indices and 8 segments.
77 00000014 ;
78 00000014 ;
79 00000014 ; Syntax:
80 00000014 ; void FlushDCache(void);
81 00000014 ;
82 00000014 ; Arguments:
83 00000014 ; -- none --
84 00000014 ;
85 00000014 ; Return Value:
86 00000014 ; -- none --
87 00000014 ; r0..r2 junk
88 00000014 ; CC flags junk
89 00000014 ;--
90 00000014
91 00000014 e3a01040 mov r1, #64 ; Set the index loop counter
92 00000018 30
93 00000018 e3a00000 mov r0, #0
94 0000001c e1800d01 orr r0, r0, r1, LSL #26
95 00000020 ee070f5e mcr p15, 0, r0, c7, c14, 2 ; clean index in r1, segment 0
96 00000024 e3800020 orr r0, r0, #0x20
97 00000028 ee070f5e mcr p15, 0, r0, c7, c14, 2 ; clean index r1, segment 1
98 0000002c e3800060 orr r0, r0, #0x60
99 00000030 ee070f5e mcr p15, 0, r0, c7, c14, 2 ; clean index r1, segment 3
100 00000034 e38000e0 orr r0, r0, #0xe0
101 00000038 ee070f5e mcr p15, 0, r0, c7, c14, 2 ; clean index r1, segment 7
102 0000003c e3c00040 bic r0, r0, #0x40
103 00000040 ee070f5e mcr p15, 0, r0, c7, c14, 2 ; clean index r1, segment 5
104 00000044 e3c00020 bic r0, r0, #0x20
105 00000048 ee070f5e mcr p15, 0, r0, c7, c14, 2 ; clean index r1, segment 4
106 0000004c e38000c0 orr r0, r0, #0xc0
107 00000050 ee070f5e mcr p15, 0, r0, c7, c14, 2 ; clean index r1, segment 6
108 00000054 e3c00080 bic r0, r0, #0x80
109 00000058 ee070f5e mcr p15, 0, r0, c7, c14, 2 ; clean index r1, segment 2
110 0000005c
111 0000005c e2511001 subs r1, r1, #1
112 00000060 1affffec bne %b30
113 00000064
114 00000064 IF Thumbing
116 00000064 ELSE
117 00000064 e1a0f00e mov pc, lr ; return
118 00000068 ENDIF
119 00000068
120 00000068
121 00000068 LEAF_ENTRY OEMARMCacheMode
122 00000068 ;++
123 00000068 ; Routine Description:
124 00000068 ; Sets the C and B bits to be used to build page tables
125 00000068 ;
126 00000068 ; C and B bits are part of the page table entries and control write through vs. write back cache
127 00000068 ; modes, cacheability, and write buffer use. Note that C and B bit functionality is processor
128 00000068 ; specific and different for the 720, 920, and SA1100. Consult the CPU hardware manual for the CPU
129 00000068 ; in question before altering these bit configurations!!
130 00000068 ; This default configuration (C=B=1)works on all current ARM CPU's and gives the following behaviour
131 00000068 ; ARM720: write through, write buffer enabled
132 00000068 ; ARM920: write back cache mode
133 00000068 ; SA1100: write back, write buffer enabled
134 00000068 ;
135 00000068 ; The four valid options are:
136 00000068 ; ARM_NoBits 0x00000000
137 00000068 ; ARM_CBit 0x00000008
138 00000068 ; ARM_BBit 0x00000004
139 00000068 ; ARM_CBBits 0x0000000C
140 00000068 ;
141 00000068 ; Syntax:
142 00000068 ; DWORD OEMARMCacheMode(void);
143 00000068 ;
144 00000068 ; Arguments:
145 00000068 ; -- none --
146 00000068 ;
147 00000068 ; Return Value:
148 00000068 ; r0 must contain the desired C and B bit configuration. See description above for valid bit patterns.
149 00000068 ;
150 00000068 ; Caution:
151 00000068 ; The value placed in r0 MUST be an immediate data value and NOT a predefined constant. This function
152 00000068 ; is called at a point in the boot cycle where the memory containing predefined constants has NOT been
153 00000068 ; initialized yet.
154 00000068 ;--
155 00000068 e3a0000c mov r0, #0x0000000C
156 0000006c
157 0000006c IF Thumbing
159 0000006c ELSE
160 0000006c e1a0f00e mov pc, lr ; return
161 00000070 ENDIF
162 00000070
163 00000070 END
Assembly terminated, errors: 0, warnings: 0
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