📄 ds8007.lst
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501 1 }
502
503 /*
504 Send a message using T=0 or T=1 protocol
505 */
506 int16_t dssc_sendAPDU(uint8_t *buffer,int16_t length,uint8_t *rbuffer)
507 {
508 1 switch (TMode[currentSlot])
509 1 {
510 2 case 0:
511 2 return dssc_sendAPDUT0(buffer,length,rbuffer);
512 2 break;
513 2 case 1:
514 2 return dssc_sendAPDUT1(buffer,length,rbuffer);
515 2 break;
516 2 default:
517 2 return ERR_PROTOCOL_UNSUPPORTED;
518 2 break;
519 2 }
520 1 }
521
522 int16_t dssc_warmreset(uint8_t mode)
523 {
524 1 uint8_t val;
525 1
526 1 // Check for power status
527 1 val = dssc_readregister(PCR);
528 1 if (!(val & PCR_START_MASK))
529 1 return ERR_POWERUP_VOLTAGE_INVALID;
530 1
531 1 // Apply reset
532 1 val = dssc_readregister(PCR);
533 1 dssc_writeregister(PCR,val & ~PCR_RSTIN_MASK);
534 1
535 1 // Call common getATR routine
536 1 return dssc_ATRsequence(mode);
537 1 }
538
539 int16_t dssc_powerup(uint8_t mode, uint8_t voltage)
540 {
541 1 uint8_t val;
542 1
543 1 // Compile time setting of operating crystal frequency
544 1 #if ((CRYSTAL_FREQUENCY_8007 >= 1000000L) && (CRYSTAL_FREQUENCY_8007 <= 5000000L))
// Set smartcard clock to 1/1 crystal
dssc_writeregister(CCR,0x00);
#elif ((CRYSTAL_FREQUENCY_8007 >= 2000000L) && (CRYSTAL_FREQUENCY_8007 <= 10000000L))
// Set smartcard clock to 1/2 crystal
dssc_writeregister(CCR,0x01);
#elif ((CRYSTAL_FREQUENCY_8007 >= 4000000L) && (CRYSTAL_FREQUENCY_8007 <= 20000000L))
C51 COMPILER V8.08 DS8007 10/26/2007 09:32:25 PAGE 10
551 1 // Set smartcard clock to 1/4 crystal
552 1 dssc_writeregister(CCR,0x02);
553 1 #elif ((CRYSTAL_FREQUENCY_8007 >= 8000000L) && (CRYSTAL_FREQUENCY_8007 <= 40000000L))
// Set smartcard clock to 1/8 crystal
dssc_writeregister(CCR,0x03);
#else
// Set smartcard clock to 1/2 internal oscillator (about 1.44MHz)
// NOTE: Can only change CCR.2 when shifting to internal oscillator
dssc_writeregister(CCR,0x01);
dssc_writeregister(CCR,0x05);
// Wait for internal oscillator to engage (check the MSR.CLKSW bit on page 18)
do
{
val = dssc_readregister(MSR);
}
while (!(val & MSR_CLKSW_MASK));
#endif
569 1
570 1 // Set the power supply voltage
571 1 val = dssc_readregister(PCR);
572 1 // Clear 1.8V and 3V bits
573 1 dssc_writeregister(PCR,val & ~(PCR_3V_5V_MASK|PCR_1V8_MASK));
574 1 switch(voltage)
575 1 {
576 2 case POWERUP_5V:
577 2 // Do nothing
578 2 break;
579 2 case POWERUP_3V:
580 2 val = dssc_readregister(PCR);
581 2 // Set 3V bit
582 2 dssc_writeregister(PCR,val | PCR_3V_5V_MASK);
583 2 break;
584 2 case POWERUP_1p8V:
585 2 val = dssc_readregister(PCR);
586 2 // Set 1.8V bit
587 2 dssc_writeregister(PCR,val | PCR_1V8_MASK);
588 2 break;
589 2 default:
590 2 return ERR_POWERUP_VOLTAGE_INVALID;
591 2 break;
592 2 }
593 1
594 1 // Apply reset
595 1 val = dssc_readregister(PCR);
596 1 dssc_writeregister(PCR,val & ~PCR_RSTIN_MASK);
597 1
598 1 val = dssc_readregister(HSR);
599 1 do
600 1 {
601 2 // Power the card, RST low, C4 and C8 high
602 2 val = dssc_readregister(PCR);
603 2 dssc_writeregister(PCR,val | (PCR_C8_MASK|PCR_C4_MASK|PCR_START_MASK));
604 2 val = dssc_readregister(HSR);
605 2 if (val & (HSR_PRTL2_MASK|HSR_PRTL1_MASK|HSR_PRL2_MASK|HSR_PRL1_MASK|HSR_PTL_MASK))
606 2 {
607 3 dssc_powerdown();
608 3 return ERR_POWERUP_INTERRUPTED;
609 3 }
610 2 val = dssc_readregister(PCR);
611 2
612 2 }
C51 COMPILER V8.08 DS8007 10/26/2007 09:32:25 PAGE 11
613 1 while (!(val & PCR_START_MASK));
614 1
615 1 //return 1;
616 1
617 1 // Call common getATR routine
618 1 return dssc_ATRsequence(mode);
619 1 }
620
621 int16_t dssc_ATRsequence(uint8_t mode)
622 {
623 1 uint8_t val;
624 1 uint8_t USRval;
625 1 uint8_t index;
626 1 uint8_t etucount = 0;
627 1 int16_t i;
628 1 uint8_t historicalBytes;
629 1 uint8_t expectedCharacters;
630 1 uint8_t interfaceIteration = 1;
631 1 uint8_t done = 0;
632 1 uint8_t check;
633 1 // Default to T=0 mode
634 1 uint8_t T = 0;
635 1 uint8_t curByte;
636 1
637 1 clearATRStruct(&lastATR[currentSlot]);
638 1 NAD[currentSlot] = 0;
639 1
640 1 // Reset the UART
641 1 val = dssc_readregister(CSR);
642 1 dssc_writeregister(CSR,val & ~CSR_nRIU_MASK);
643 1 // Remove UART reset
644 1 val = dssc_readregister(CSR);
645 1 dssc_writeregister(CSR,val | CSR_nRIU_MASK);
646 1 // Set FIFO to 1 byte
647 1 dssc_writeregister(FCR,0x00);
648 1 // Set divisor
649 1 dssc_writeregister(PDR,12);
650 1 // Set prescaler
651 1 dssc_writeregister(UCR2,0x00);
652 1
653 1 // Enable auto convention
654 1 val = dssc_readregister(UCR2);
655 1 dssc_writeregister(UCR2,val & ~UCR2_nAUTOCONV_MASK);
656 1
657 1 // Set SS bit
658 1 dssc_writeregister(UCR1,UCR1_SS_MASK);
659 1
660 1 // Wait 40000 to 45000 cycles to release reset
661 1 dssc_writeregister(TOC,0x00);
662 1 dssc_writeregister(TOR3,0x00);
663 1 dssc_writeregister(TOR2,0x6C);
664 1 dssc_writeregister(TOR1,0x00);
665 1 dssc_writeregister(TOC,0x61);
666 1
667 1 do
668 1 {
669 2 val = dssc_readregister(USR);
670 2 }
671 1 while (!(val & USR_TOL3_MASK));
672 1
673 1 if (mode == POWERUP_ISO)
674 1 {
C51 COMPILER V8.08 DS8007 10/26/2007 09:32:25 PAGE 12
675 2 // Wait up to 40000 cycles for ATR to start
676 2 dssc_writeregister(TOC,0x00);
677 2 dssc_writeregister(TOR3,0x00);
678 2 dssc_writeregister(TOR2,0x78);
679 2 dssc_writeregister(TOR1,0x00);
680 2 dssc_writeregister(TOC,0x61);
681 2 }
682 1 else // power up EMV
683 1 {
684 2 // Wait up to 40000 cycles for ATR to start and 19200 etu counter after first byte
685 2 dssc_writeregister(TOC,0x00);
686 2 dssc_writeregister(TOR3,0x00);
687 2 dssc_writeregister(TOR2,0x78);
688 2 dssc_writeregister(TOR1,0xC0);
689 2 dssc_writeregister(TOC,0x65);
690 2 }
691 1
692 1 // Release reset
693 1 val = dssc_readregister(PCR);
694 1 dssc_writeregister(PCR,val | PCR_RSTIN_MASK);
695 1
696 1 while (1)
697 1 {
698 2 val = dssc_readregister(MSR);
699 2 // If we see the first character come in, break.
700 2 if (val & MSR_TBE_RBF_MASK)
701 2 break;
702 2
703 2 val = dssc_readregister(USR);
704 2
705 2 if (val & (USR_PE_MASK|USR_FER_MASK|USR_OVR_MASK|USR_EA_MASK))
706 2 {
707 3 dssc_powerdown();
708 3 return ERR_POWERUP_ATR_INVALID;
709 3 }
710 2 if (val & USR_TOL3_MASK)
711 2 {
712 3 dssc_powerdown();
713 3 return ERR_POWERUP_ATR_TIMEOUT;
714 3 }
715 2 }
716 1
717 1 if (mode == POWERUP_ISO)
718 1 {
719 2 // Set up timer for 9600 etu between characters in ATR
720 2 dssc_writeregister(TOC,0x00);
721 2 dssc_writeregister(TOR3,0x25);
722 2 dssc_writeregister(TOR2,0x80);
723 2 dssc_writeregister(TOR1,0x00);
724 2 // Start timer
725 2 dssc_writeregister(TOC,0x61);
726 2 }
727 1 else // mode is EMV
728 1 {
729 2 // Set up timer for 9600 etu between characters in ATR, and
730 2 // maximum of 19200 etu for whole ATR
731 2 dssc_writeregister(TOC,0x05);
732 2 dssc_writeregister(TOR3,0x25);
733 2 dssc_writeregister(TOR2,0x80);
734 2 dssc_writeregister(TOR1,0xC0);
735 2 // Start timer
736 2 dssc_writeregister(TOC,0x65);
C51 COMPILER V8.08 DS8007 10/26/2007 09:32:25 PAGE 13
737 2 }
738 1
739 1 index = 0;
740 1
741 1 while (!done)
742 1 {
743 2 // Read UART status
744 2 USRval = dssc_readregister(USR);
745 2 {
746 3 // If receive buffer full
747 3 if (USRval & USR_TBE_RBF_MASK)
748 3 {
749 4 // Read and store ATR byte
750 4 val = dssc_readregister(URR);
751 4 curByte = val;
752 4 workingBuffer[index++] = val;
753 4 if (index == 1)
754 4 {
755 5 lastATR[currentSlot].TS = curByte;
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