magic-boot-2440-v1.0.patch

三星2440,超強bootloader,使用vivi下去做修改的.....歡迎使用

+ */
+
+/************************************************
+ * NAME	    : s3c2410.h
+ * Version  : 31.3.2003
+ *
+ * Based on S3C2410X User's manual Rev 1.1
+ ************************************************/
+
+#ifndef __S3C2440_H__
+#define __S3C2440_H__
+
+#define S3C24X0_UART_CHANNELS	3
+#define S3C24X0_SPI_CHANNELS	2
+
+/* S3C2410 only supports 512 Byte HW ECC */
+#define S3C2410_ECCSIZE		512
+#define S3C2410_ECCBYTES	3
+
+typedef enum {
+	S3C24X0_UART0,
+	S3C24X0_UART1,
+	S3C24X0_UART2
+} S3C24X0_UARTS_NR;
+
+/* S3C2410 device base addresses */
+#define S3C24X0_MEMCTL_BASE		0x48000000
+#define S3C24X0_USB_HOST_BASE		0x49000000
+#define S3C24X0_INTERRUPT_BASE		0x4A000000
+#define S3C24X0_DMA_BASE		0x4B000000
+#define S3C24X0_CLOCK_POWER_BASE	0x4C000000
+#define S3C24X0_LCD_BASE		0x4D000000
+#define S3C2410_NAND_BASE		0x4E000000
+#define S3C24X0_UART_BASE		0x50000000
+#define S3C24X0_TIMER_BASE		0x51000000
+#define S3C24X0_USB_DEVICE_BASE		0x52000140
+#define S3C24X0_WATCHDOG_BASE		0x53000000
+#define S3C24X0_I2C_BASE		0x54000000
+#define S3C24X0_I2S_BASE		0x55000000
+#define S3C24X0_GPIO_BASE		0x56000000
+#define S3C24X0_RTC_BASE		0x57000000
+#define S3C2410_ADC_BASE		0x58000000
+#define S3C24X0_SPI_BASE		0x59000000
+#define S3C2410_SDI_BASE		0x5A000000
+
+
+/* include common stuff */
+#include <s3c24x0.h>
+
+
+static inline S3C24X0_MEMCTL * const S3C24X0_GetBase_MEMCTL(void)
+{
+	return (S3C24X0_MEMCTL * const)S3C24X0_MEMCTL_BASE;
+}
+static inline S3C24X0_USB_HOST * const S3C24X0_GetBase_USB_HOST(void)
+{
+	return (S3C24X0_USB_HOST * const)S3C24X0_USB_HOST_BASE;
+}
+static inline S3C24X0_INTERRUPT * const S3C24X0_GetBase_INTERRUPT(void)
+{
+	return (S3C24X0_INTERRUPT * const)S3C24X0_INTERRUPT_BASE;
+}
+static inline S3C24X0_DMAS * const S3C24X0_GetBase_DMAS(void)
+{
+	return (S3C24X0_DMAS * const)S3C24X0_DMA_BASE;
+}
+static inline S3C24X0_CLOCK_POWER * const S3C24X0_GetBase_CLOCK_POWER(void)
+{
+	return (S3C24X0_CLOCK_POWER * const)S3C24X0_CLOCK_POWER_BASE;
+}
+static inline S3C24X0_LCD * const S3C24X0_GetBase_LCD(void)
+{
+	return (S3C24X0_LCD * const)S3C24X0_LCD_BASE;
+}
+static inline S3C2410_NAND * const S3C2410_GetBase_NAND(void)
+{
+	return (S3C2410_NAND * const)S3C2410_NAND_BASE;
+}
+static inline S3C2440_NAND * const S3C2440_GetBase_NAND(void)
+{
+	return (S3C2440_NAND * const)S3C2440_NAND_BASE;
+}
+static inline S3C24X0_UART * const S3C24X0_GetBase_UART(S3C24X0_UARTS_NR nr)
+{
+	return (S3C24X0_UART * const)(S3C24X0_UART_BASE + (nr * 0x4000));
+}
+static inline S3C24X0_TIMERS * const S3C24X0_GetBase_TIMERS(void)
+{
+	return (S3C24X0_TIMERS * const)S3C24X0_TIMER_BASE;
+}
+static inline S3C24X0_USB_DEVICE * const S3C24X0_GetBase_USB_DEVICE(void)
+{
+	return (S3C24X0_USB_DEVICE * const)S3C24X0_USB_DEVICE_BASE;
+}
+static inline S3C24X0_WATCHDOG * const S3C24X0_GetBase_WATCHDOG(void)
+{
+	return (S3C24X0_WATCHDOG * const)S3C24X0_WATCHDOG_BASE;
+}
+static inline S3C24X0_I2C * const S3C24X0_GetBase_I2C(void)
+{
+	return (S3C24X0_I2C * const)S3C24X0_I2C_BASE;
+}
+static inline S3C24X0_I2S * const S3C24X0_GetBase_I2S(void)
+{
+	return (S3C24X0_I2S * const)S3C24X0_I2S_BASE;
+}
+static inline S3C24X0_GPIO * const S3C24X0_GetBase_GPIO(void)
+{
+	return (S3C24X0_GPIO * const)S3C24X0_GPIO_BASE;
+}
+static inline S3C24X0_RTC * const S3C24X0_GetBase_RTC(void)
+{
+	return (S3C24X0_RTC * const)S3C24X0_RTC_BASE;
+}
+static inline S3C2410_ADC * const S3C2410_GetBase_ADC(void)
+{
+	return (S3C2410_ADC * const)S3C2410_ADC_BASE;
+}
+static inline S3C2440_ADC * const S3C2440_GetBase_ADC(void)
+{
+	return (S3C2440_ADC * const)S3C2440_ADC_BASE;
+}
+static inline S3C24X0_SPI * const S3C24X0_GetBase_SPI(void)
+{
+	return (S3C24X0_SPI * const)S3C24X0_SPI_BASE;
+}
+static inline S3C2410_SDI * const S3C2410_GetBase_SDI(void)
+{
+	return (S3C2410_SDI * const)S3C2410_SDI_BASE;
+}
+
+
+/* ISR */
+#define pISR_RESET		(*(unsigned *)(_ISR_STARTADDRESS+0x0))
+#define pISR_UNDEF		(*(unsigned *)(_ISR_STARTADDRESS+0x4))
+#define pISR_SWI		(*(unsigned *)(_ISR_STARTADDRESS+0x8))
+#define pISR_PABORT		(*(unsigned *)(_ISR_STARTADDRESS+0xC))
+#define pISR_DABORT		(*(unsigned *)(_ISR_STARTADDRESS+0x10))
+#define pISR_RESERVED		(*(unsigned *)(_ISR_STARTADDRESS+0x14))
+#define pISR_IRQ		(*(unsigned *)(_ISR_STARTADDRESS+0x18))
+#define pISR_FIQ		(*(unsigned *)(_ISR_STARTADDRESS+0x1C))
+
+#define pISR_EINT0		(*(unsigned *)(_ISR_STARTADDRESS+0x20))
+#define pISR_EINT1		(*(unsigned *)(_ISR_STARTADDRESS+0x24))
+#define pISR_EINT2		(*(unsigned *)(_ISR_STARTADDRESS+0x28))
+#define pISR_EINT3		(*(unsigned *)(_ISR_STARTADDRESS+0x2C))
+#define pISR_EINT4_7		(*(unsigned *)(_ISR_STARTADDRESS+0x30))
+#define pISR_EINT8_23		(*(unsigned *)(_ISR_STARTADDRESS+0x34))
+#define pISR_BAT_FLT		(*(unsigned *)(_ISR_STARTADDRESS+0x3C))
+#define pISR_TICK		(*(unsigned *)(_ISR_STARTADDRESS+0x40))
+#define pISR_WDT		(*(unsigned *)(_ISR_STARTADDRESS+0x44))
+#define pISR_TIMER0		(*(unsigned *)(_ISR_STARTADDRESS+0x48))
+#define pISR_TIMER1		(*(unsigned *)(_ISR_STARTADDRESS+0x4C))
+#define pISR_TIMER2		(*(unsigned *)(_ISR_STARTADDRESS+0x50))
+#define pISR_TIMER3		(*(unsigned *)(_ISR_STARTADDRESS+0x54))
+#define pISR_TIMER4		(*(unsigned *)(_ISR_STARTADDRESS+0x58))
+#define pISR_UART2		(*(unsigned *)(_ISR_STARTADDRESS+0x5C))
+#define pISR_NOTUSED		(*(unsigned *)(_ISR_STARTADDRESS+0x60))
+#define pISR_DMA0		(*(unsigned *)(_ISR_STARTADDRESS+0x64))
+#define pISR_DMA1		(*(unsigned *)(_ISR_STARTADDRESS+0x68))
+#define pISR_DMA2		(*(unsigned *)(_ISR_STARTADDRESS+0x6C))
+#define pISR_DMA3		(*(unsigned *)(_ISR_STARTADDRESS+0x70))
+#define pISR_SDI		(*(unsigned *)(_ISR_STARTADDRESS+0x74))
+#define pISR_SPI0		(*(unsigned *)(_ISR_STARTADDRESS+0x78))
+#define pISR_UART1		(*(unsigned *)(_ISR_STARTADDRESS+0x7C))
+#define pISR_USBD		(*(unsigned *)(_ISR_STARTADDRESS+0x84))
+#define pISR_USBH		(*(unsigned *)(_ISR_STARTADDRESS+0x88))
+#define pISR_IIC		(*(unsigned *)(_ISR_STARTADDRESS+0x8C))
+#define pISR_UART0		(*(unsigned *)(_ISR_STARTADDRESS+0x90))
+#define pISR_SPI1		(*(unsigned *)(_ISR_STARTADDRESS+0x94))
+#define pISR_RTC		(*(unsigned *)(_ISR_STARTADDRESS+0x98))
+#define pISR_ADC		(*(unsigned *)(_ISR_STARTADDRESS+0xA0))
+
+
+/* PENDING BIT */
+#define BIT_EINT0		(0x1)
+#define BIT_EINT1		(0x1<<1)
+#define BIT_EINT2		(0x1<<2)
+#define BIT_EINT3		(0x1<<3)
+#define BIT_EINT4_7		(0x1<<4)
+#define BIT_EINT8_23		(0x1<<5)
+#define BIT_BAT_FLT		(0x1<<7)
+#define BIT_TICK		(0x1<<8)
+#define BIT_WDT			(0x1<<9)
+#define BIT_TIMER0		(0x1<<10)
+#define BIT_TIMER1		(0x1<<11)
+#define BIT_TIMER2		(0x1<<12)
+#define BIT_TIMER3		(0x1<<13)
+#define BIT_TIMER4		(0x1<<14)
+#define BIT_UART2		(0x1<<15)
+#define BIT_LCD			(0x1<<16)
+#define BIT_DMA0		(0x1<<17)
+#define BIT_DMA1		(0x1<<18)
+#define BIT_DMA2		(0x1<<19)
+#define BIT_DMA3		(0x1<<20)
+#define BIT_SDI			(0x1<<21)
+#define BIT_SPI0		(0x1<<22)
+#define BIT_UART1		(0x1<<23)
+#define BIT_USBD		(0x1<<25)
+#define BIT_USBH		(0x1<<26)
+#define BIT_IIC			(0x1<<27)
+#define BIT_UART0		(0x1<<28)
+#define BIT_SPI1		(0x1<<29)
+#define BIT_RTC			(0x1<<30)
+#define BIT_ADC			(0x1<<31)
+#define BIT_ALLMSK		(0xFFFFFFFF)
+
+#define ClearPending(bit) {\
+		 rSRCPND = bit;\
+		 rINTPND = bit;\
+		 rINTPND;\
+		 }
+/* Wait until rINTPND is changed for the case that the ISR is very short. */
+#endif /*__S3C2410_H__*/
diff -Nur u-boot-1.2.0/include/s3c24x0.h magic-boot-2440-v1.0/include/s3c24x0.h
--- u-boot-1.2.0/include/s3c24x0.h	2007-01-07 07:13:11.000000000 +0800
+++ magic-boot-2440-v1.0/include/s3c24x0.h	2007-06-29 16:09:56.000000000 +0800
@@ -82,7 +82,7 @@
 	S3C24X0_REG32	PRIORITY;
 	S3C24X0_REG32	INTPND;
 	S3C24X0_REG32	INTOFFSET;
-#ifdef CONFIG_S3C2410
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
 	S3C24X0_REG32	SUBSRCPND;
 	S3C24X0_REG32	INTSUBMSK;
 #endif
@@ -92,11 +92,11 @@
 /* DMAS (see manual chapter 8) */
 typedef struct {
 	S3C24X0_REG32	DISRC;
-#ifdef CONFIG_S3C2410
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
 	S3C24X0_REG32	DISRCC;
 #endif
 	S3C24X0_REG32	DIDST;
-#ifdef CONFIG_S3C2410
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
 	S3C24X0_REG32	DIDSTC;
 #endif
 	S3C24X0_REG32	DCON;
@@ -107,7 +107,7 @@
 #ifdef CONFIG_S3C2400
 	S3C24X0_REG32	res[1];
 #endif
-#ifdef CONFIG_S3C2410
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
 	S3C24X0_REG32	res[7];
 #endif
 } /*__attribute__((__packed__))*/ S3C24X0_DMA;
@@ -126,6 +126,9 @@
 	S3C24X0_REG32	CLKCON;
 	S3C24X0_REG32	CLKSLOW;
 	S3C24X0_REG32	CLKDIVN;
+#ifdef CONFIG_S3C2440
+	S3C24X0_REG32	CAMDIVN;
+#endif
 } /*__attribute__((__packed__))*/ S3C24X0_CLOCK_POWER;
 
 
@@ -145,7 +148,7 @@
 	S3C24X0_REG32	res[8];
 	S3C24X0_REG32	DITHMODE;
 	S3C24X0_REG32	TPAL;
-#ifdef CONFIG_S3C2410
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
 	S3C24X0_REG32	LCDINTPND;
 	S3C24X0_REG32	LCDSRCPND;
 	S3C24X0_REG32	LCDINTMSK;
@@ -157,6 +160,9 @@
 /* NAND FLASH (see S3C2410 manual chapter 6) */
 typedef struct {
 	S3C24X0_REG32	NFCONF;
+#ifdef CONFIG_S3C2440
+	S3C24X0_REG32	NFCONT;
+#endif
 	S3C24X0_REG32	NFCMD;
 	S3C24X0_REG32	NFADDR;
 	S3C24X0_REG32	NFDATA;
@@ -164,6 +170,18 @@
 	S3C24X0_REG32	NFECC;
 } /*__attribute__((__packed__))*/ S3C2410_NAND;
 
+/* NAND FLASH (see S3C2410 manual chapter 6) */
+typedef struct {
+	S3C24X0_REG32	NFCONF;
+#ifdef CONFIG_S3C2440
+	S3C24X0_REG32	NFCONT;
+#endif
+	S3C24X0_REG32	NFCMD;
+	S3C24X0_REG32	NFADDR;
+	S3C24X0_REG32	NFDATA;
+	S3C24X0_REG32	NFSTAT;
+	S3C24X0_REG32	NFECC;
+} /*__attribute__((__packed__))*/ S3C2440_NAND;
 
 /* UART (see manual chapter 11) */
 typedef struct {
@@ -451,6 +469,65 @@
 	S3C24X0_REG32	GSTATUS3;
 	S3C24X0_REG32	GSTATUS4;
 #endif
+#ifdef CONFIG_S3C2440
+	S3C24X0_REG32	GPACON;
+	S3C24X0_REG32	GPADAT;
+	S3C24X0_REG32	res1[2];
+	S3C24X0_REG32	GPBCON;
+	S3C24X0_REG32	GPBDAT;
+	S3C24X0_REG32	GPBUP;
+	S3C24X0_REG32	res2;
+	S3C24X0_REG32	GPCCON;
+	S3C24X0_REG32	GPCDAT;
+	S3C24X0_REG32	GPCUP;
+	S3C24X0_REG32	res3;
+	S3C24X0_REG32	GPDCON;
+	S3C24X0_REG32	GPDDAT;
+	S3C24X0_REG32	GPDUP;
+	S3C24X0_REG32	res4;
+	S3C24X0_REG32	GPECON;
+	S3C24X0_REG32	GPEDAT;
+	S3C24X0_REG32	GPEUP;
+	S3C24X0_REG32	res5;
+	S3C24X0_REG32	GPFCON;
+	S3C24X0_REG32	GPFDAT;
+	S3C24X0_REG32	GPFUP;
+	S3C24X0_REG32	res6;
+	S3C24X0_REG32	GPGCON;
+	S3C24X0_REG32	GPGDAT;
+	S3C24X0_REG32	GPGUP;
+	S3C24X0_REG32	res7;
+	S3C24X0_REG32	GPHCON;
+	S3C24X0_REG32	GPHDAT;
+	S3C24X0_REG32	GPHUP;
+	S3C24X0_REG32	res8;
+
+	S3C24X0_REG32	MISCCR;
+	S3C24X0_REG32	DCLKCON;
+	S3C24X0_REG32	EXTINT0;
+	S3C24X0_REG32	EXTINT1;
+	S3C24X0_REG32	EXTINT2;
+	S3C24X0_REG32	EINTFLT0;
+	S3C24X0_REG32	EINTFLT1;
+	S3C24X0_REG32	EINTFLT2;
+	S3C24X0_REG32	EINTFLT3;
+	S3C24X0_REG32	EINTMASK;
+	S3C24X0_REG32	EINTPEND;
+	S3C24X0_REG32	GSTATUS0;
+	S3C24X0_REG32	GSTATUS1;
+	S3C24X0_REG32	GSTATUS2;
+	S3C24X0_REG32	GSTATUS3;
+	S3C24X0_REG32	GSTATUS4;
+
+	S3C24X0_REG32	res9;
+	S3C24X0_REG32	DSC0;
+	S3C24X0_REG32	DSC1;
+	S3C24X0_REG32	MSLCON;
+	S3C24X0_REG32	GPJCON;
+	S3C24X0_REG32	GPJDAT;
+	S3C24X0_REG32	GPJUP;
+	S3C24X0_REG32	res10;
+#endif
 } /*__attribute__((__packed__))*/ S3C24X0_GPIO;
 
 
@@ -547,6 +624,14 @@
 	S3C24X0_REG32	ADCDAT1;
 } /*__attribute__((__packed__))*/ S3C2410_ADC;
 
+/* ADC (see manual chapter 16) */
+typedef struct {
+	S3C24X0_REG32	ADCCON;
+	S3C24X0_REG32	ADCTSC;
+	S3C24X0_REG32	ADCDLY;
+	S3C24X0_REG32	ADCDAT0;
+	S3C24X0_REG32	ADCDAT1;
+} /*__attribute__((__packed__))*/ S3C2440_ADC;
 
 /* SPI (see manual chapter 22) */
 typedef struct {
@@ -637,14 +722,15 @@
 	S3C24X0_REG32	SDIDCNT;
 	S3C24X0_REG32	SDIDSTA;
 	S3C24X0_REG32	SDIFSTA;
-#ifdef __BIG_ENDIAN
-	S3C24X0_REG8	res[3];
+#ifdef CONFIG_S3C2410
 	S3C24X0_REG8	SDIDAT;
-#else
+	S3C24X0_REG32	SDIIMSK;
+	S3C24X0_REG8	res[3];
+#elif  CONFIG_S3C2440
+	S3C24X0_REG32	SDIIMSK;
 	S3C24X0_REG8	SDIDAT;
 	S3C24X0_REG8	res[3];
 #endif
-	S3C24X0_REG32	SDIIMSK;
 } /*__attribute__((__packed__))*/ S3C2410_SDI;
 
 
diff -Nur u-boot-1.2.0/lib_arm/board.c magic-boot-2440-v1.0/lib_arm/board.c
--- u-boot-1.2.0/lib_arm/board.c	2007-01-07 07:13:11.000000000 +0800
+++ magic-boot-2440-v1.0/lib_arm/board.c	2007-06-29 17:23:32.000000000 +0800
@@ -52,6 +52,8 @@
 #include "../drivers/lan91c96.h"
 #endif
 
+#define DEBUG
+
 DECLARE_GLOBAL_DATA_PTR;
 
 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
diff -Nur u-boot-1.2.0/Makefile magic-boot-2440-v1.0/Makefile
--- u-boot-1.2.0/Makefile	2007-01-07 07:13:11.000000000 +0800
+++ magic-boot-2440-v1.0/Makefile	2007-06-29 13:42:18.000000000 +0800
@@ -125,7 +125,7 @@
 CROSS_COMPILE = powerpc-linux-
 endif
 ifeq ($(ARCH),arm)
-CROSS_COMPILE = arm-linux-
+CROSS_COMPILE = /usr/local/arm/3.3.2/bin/arm-linux-
 endif
 ifeq ($(ARCH),i386)
 ifeq ($(HOSTARCH),i386)
@@ -236,7 +236,7 @@
 #########################################################################
 #########################################################################
 
-ALL = $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND)
+ALL = $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND)$(obj)u-boot.img
 
 all:		$(ALL)
 
@@ -1922,6 +1922,9 @@
 smdk2410_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm920t smdk2410 NULL s3c24x0
 
+max2440p_config	:	unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm920t max2440p NULL s3c24x0
+
 SX1_config :		unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm925t sx1
 
diff -Nur u-boot-1.2.0/rtc/s3c24x0_rtc.c magic-boot-2440-v1.0/rtc/s3c24x0_rtc.c
--- u-boot-1.2.0/rtc/s3c24x0_rtc.c	2007-01-07 07:13:11.000000000 +0800
+++ magic-boot-2440-v1.0/rtc/s3c24x0_rtc.c	2007-06-29 15:02:35.000000000 +0800
@@ -34,6 +34,8 @@
 #include <s3c2400.h>
 #elif defined(CONFIG_S3C2410)
 #include <s3c2410.h>
+#elif defined(CONFIG_S3C2440)
+#include <s3c2440.h>
 #endif
 
 #include <rtc.h>