custom_ram2port.vhd

基于FPGA的音频分析仪

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY custom_ram2port IS
  PORT(  
 -- avalone bus common port
       CLK       :IN  STD_LOGIC;--模块时钟32M
       write_n   :IN  STD_LOGIC;--写信号
       read_n    :IN  STD_LOGIC;--读信号
       chipselect:IN  STD_LOGIC;--片选
       address   :IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
       writedata :IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
       readdata  :OUT STD_LOGIC_VECTOR(31 DOWNTO 0);   
----out CPU
       EXP:        IN STD_LOGIC_VECTOR(5 DOWNTO 0);
       RAM_WREN   :OUT STD_LOGIC;
	   RAM_RDEN   :OUT STD_LOGIC;
       RAM_WR_CLOCK  :OUT STD_LOGIC;
       RAM_RD_CLOCK  :OUT STD_LOGIC;
       RAM_WR_ADDRESS:OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
       RAM_RD_ADDRESS:OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
       RAM_Q:      IN STD_LOGIC_VECTOR(31 DOWNTO 0);
       RAM_DATA   :OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
END; 
ARCHITECTURE RTL OF custom_ram2port IS

BEGIN 
----avalone总线读写------------------------------------------------------
PROCESS(CHIPSELECT,write_n,read_n,CLK,address,writedata)
   BEGIN
     IF  CLK'EVENT AND CLK='1' THEN
          IF  CHIPSELECT='1' THEN 
              IF write_n='0' THEN 
	             CASE address IS   
                    WHEN "0000"=>RAM_WREN<='0';
                                 RAM_RD_CLOCK<='0';
                                 RAM_WR_CLOCK<='0';
	                WHEN "0001"=>RAM_WREN<='1';
	                WHEN "0010"=>RAM_WR_ADDRESS<=writedata(9 downto 0);
	                             RAM_WR_CLOCK<='0';
	                WHEN "0011"=>RAM_DATA<=writedata;	                             
	                WHEN "0100"=>RAM_WR_CLOCK<='1';
	                WHEN "0101"=>RAM_WREN<='0';
	
	                WHEN "0110"=>RAM_RDEN<='1';
	                WHEN "0111"=>RAM_RD_ADDRESS<=writedata(9 downto 0);
	                             RAM_RD_CLOCK<='0';
	                WHEN "1000"=>RAM_RD_CLOCK<='1';
	                --IORD
	                WHEN "1001"=>RAM_RDEN<='0';
	              	WHEN OTHERS=>NULL;
	              END CASE;
                ELSIF read_n='0' THEN 
                  CASE address IS   
                    WHEN "0000"=>readdata<=RAM_Q;
                    WHEN "0001"=>readdata(5 downto 0)<=EXP;       
	            	WHEN OTHERS=>NULL;
                  END CASE;
                END IF;      
         END IF; 
    END IF;
END PROCESS;
----RAM读写--------------------------------------------------

END RTL;