hplclock.nc

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/*
 *
 * Authors:		Jason Hill, David Gay, Philip Levis
 * Date last modified:  6/25/02
 *
 */

// The hardware presentation layer. 

// The model is that HPL is stateless. If the desired interface is as stateless
// it can be implemented here (Clock, FlashBitSPI). Otherwise you should
// create a separate component
module HPLClock {
  provides interface Clock;
}
implementation
{
  command result_t Clock.setRate(char interval, char scale) {
    scale &= 0x7;
    scale |= 0x8;
    cbi(TIMSK, TOIE2);
    cbi(TIMSK, OCIE2);     //Disable TC0 interrupt
    sbi(ASSR, AS2);        //set Timer/Counter0 to be asynchronous
    //from the CPU clock with a second external
    //clock(32,768kHz)driving it.
    outp(scale, TCCR2);    //prescale the timer to be clock/128 to make it
    outp(0, TCNT2);
    outp(interval, OCR2);
    sbi(TIMSK, OCIE2); 
    while (inp(ASSR) & 0x07) { }
    return SUCCESS;
  }

  default event result_t Clock.fire() { return SUCCESS; }
  TOSH_INTERRUPT(SIG_OUTPUT_COMPARE2) {
    signal Clock.fire();
  }
}