addcon.vhd

fpga的应用

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity addcon is
   port(clk,key,control:in std_logic;
        dataout:out std_logic_vector(31 downto 0));
end addcon;
architecture behav of addcon is
signal dataa:integer range 42949 to 429496730;
signal datab:integer range 42949 to 429496730;
begin
process(key,control)
  begin
     if key'event and key='1' then
       if dataa=429496730 then 
		  dataa<=42949;
	 	else 
			case control is
             	when'0'=>dataa<=dataa+42949;
             	when'1'=>dataa<=dataa+4294978;
          	end case; 
		end if;
	end if;
	datab<=dataa;
end process;
process(clk)
  begin
    if clk'event and clk='1' then
      dataout<=conv_std_logic_vector(datab,32);
     end if;
end process;
end behav;