cnt10.vhd

来自「fpga的应用」· VHDL 代码 · 共 31 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity cnt10 is
 port(clk,key: in std_logic;
      cnt: out std_logic_vector(4 downto 0));
end cnt10;
architecture behav of cnt10 is
signal mida: integer range 0 to 10;
signal midb: integer range 0 to 10;
begin
process(key)
   begin
     if key'event and key='1' then
		if mida=10 then
		   mida<=0;
		else
		   mida<=mida+1;
		end if;
	 end if;
	midb<=mida;
end process;
process(clk)
   begin
      if clk'event and clk='1' then
		cnt<=conv_std_logic_vector(midb,5);
	  end if;
end process;
end behav;