sinsignal.map.qmsg

来自「fpga的应用」· QMSG 代码 · 共 138 行 · 第 1/5 页

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_mob_rw mysin:inst10\|mysin_st:mysin_st_inst\|asj_nco_mob_rw:ux122 " "Info: Elaborating entity \"asj_nco_mob_rw\" for hierarchy \"mysin:inst10\|mysin_st:mysin_st_inst\|asj_nco_mob_rw:ux122\"" {  } { { "mysin_st.v" "ux122" { Text "G:/study/code/eda/mysin_st.v" 214 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WCPT_DEFAULTING_TO_OPENCORE" "NCO (6AF7_0014) " "Warning: Defaulting to OpenCore or OpenCore Plus compilation for core NCO (6AF7_0014)" {  } {  } 0 0 "Defaulting to OpenCore or OpenCore Plus compilation for core %1!s!" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "D:/tools/altera/megacore/nco-v2.3.1/lib/asj_nco_isdr.v 1 1 " "Warning: Using design file D:/tools/altera/megacore/nco-v2.3.1/lib/asj_nco_isdr.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 asj_nco_isdr " "Info: Found entity 1: asj_nco_isdr" {  } { { "D:/tools/altera/megacore/nco-v2.3.1/lib/asj_nco_isdr.v" "" { Text "D:/tools/altera/megacore/nco-v2.3.1/lib/asj_nco_isdr.v" 15 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_isdr mysin:inst10\|mysin_st:mysin_st_inst\|asj_nco_isdr:ux710isdr " "Info: Elaborating entity \"asj_nco_isdr\" for hierarchy \"mysin:inst10\|mysin_st:mysin_st_inst\|asj_nco_isdr:ux710isdr\"" {  } { { "mysin_st.v" "ux710isdr" { Text "G:/study/code/eda/mysin_st.v" 234 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/tools/altera/quartus60/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/tools/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "d:/tools/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 233 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter mysin:inst10\|mysin_st:mysin_st_inst\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component " "Info: Elaborating entity \"lpm_counter\" for hierarchy \"mysin:inst10\|mysin_st:mysin_st_inst\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\"" {  } { { "D:/tools/altera/megacore/nco-v2.3.1/lib/asj_nco_isdr.v" "lpm_counter_component" { Text "D:/tools/altera/megacore/nco-v2.3.1/lib/asj_nco_isdr.v" 33 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "mysin:inst10\|mysin_st:mysin_st_inst\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component " "Info: Elaborated megafunction instantiation \"mysin:inst10\|mysin_st:mysin_st_inst\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\"" {  } { { "D:/tools/altera/megacore/nco-v2.3.1/lib/asj_nco_isdr.v" "" { Text "D:/tools/altera/megacore/nco-v2.3.1/lib/asj_nco_isdr.v" 33 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_mpf.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_mpf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_mpf " "Info: Found entity 1: cntr_mpf" {  } { { "db/cntr_mpf.tdf" "" { Text "G:/study/code/eda/db/cntr_mpf.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_mpf mysin:inst10\|mysin_st:mysin_st_inst\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\|cntr_mpf:auto_generated " "Info: Elaborating entity \"cntr_mpf\" for hierarchy \"mysin:inst10\|mysin_st:mysin_st_inst\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\|cntr_mpf:auto_generated\"" {  } { { "lpm_counter.tdf" "auto_generated" { Text "d:/tools/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 257 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "altpll1.vhd 2 1 " "Warning: Using design file altpll1.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 altpll1-SYN " "Info: Found design unit 1: altpll1-SYN" {  } { { "altpll1.vhd" "" { Text "G:/study/code/eda/altpll1.vhd" 49 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 altpll1 " "Info: Found entity 1: altpll1" {  } { { "altpll1.vhd" "" { Text "G:/study/code/eda/altpll1.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll1 altpll1:inst " "Info: Elaborating entity \"altpll1\" for hierarchy \"altpll1:inst\"" {  } { { "sinsignal.bdf" "inst" { Schematic "G:/study/code/eda/sinsignal.bdf" { { 232 160 400 408 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/tools/altera/quartus60/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/tools/altera/quartus60/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "altpll.tdf" "" { Text "d:/tools/altera/quartus60/libraries/megafunctions/altpll.tdf" 365 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll altpll1:inst\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"altpll1:inst\|altpll:altpll_component\"" {  } { { "altpll1.vhd" "altpll_component" { Text "G:/study/code/eda/altpll1.vhd" 137 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "altpll1:inst\|altpll:altpll_component " "Info: Elaborated megafunction instantiation \"altpll1:inst\|altpll:altpll_component\"" {  } { { "altpll1.vhd" "" { Text "G:/study/code/eda/altpll1.vhd" 137 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_add_sub0.vhd 2 1 " "Warning: Using design file lpm_add_sub0.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpm_add_sub0-SYN " "Info: Found design unit 1: lpm_add_sub0-SYN" {  } { { "lpm_add_sub0.vhd" "" { Text "G:/study/code/eda/lpm_add_sub0.vhd" 49 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub0 " "Info: Found entity 1: lpm_add_sub0" {  } { { "lpm_add_sub0.vhd" "" { Text "G:/study/code/eda/lpm_add_sub0.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub0 lpm_add_sub0:inst9 " "Info: Elaborating entity \"lpm_add_sub0\" for hierarchy \"lpm_add_sub0:inst9\"" {  } { { "sinsignal.bdf" "inst9" { Schematic "G:/study/code/eda/sinsignal.bdf" { { 64 600 760 160 "inst9" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub lpm_add_sub0:inst9\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"lpm_add_sub0:inst9\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "lpm_add_sub0.vhd" "lpm_add_sub_component" { Text "G:/study/code/eda/lpm_add_sub0.vhd" 72 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub0:inst9\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborated megafunction instantiation \"lpm_add_sub0:inst9\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "lpm_add_sub0.vhd" "" { Text "G:/study/code/eda/lpm_add_sub0.vhd" 72 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_0pe.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_0pe.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_0pe " "Info: Found entity 1: add_sub_0pe" {  } { { "db/add_sub_0pe.tdf" "" { Text "G:/study/code/eda/db/add_sub_0pe.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_0pe lpm_add_sub0:inst9\|lpm_add_sub:lpm_add_sub_component\|add_sub_0pe:auto_generated " "Info: Elaborating entity \"add_sub_0pe\" for hierarchy \"lpm_add_sub0:inst9\|lpm_add_sub:lpm_add_sub_component\|add_sub_0pe:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "d:/tools/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 117 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "addcon addcon:inst1 " "Info: Elaborating entity \"addcon\" for hierarchy \"addcon:inst1\"" {  } { { "sinsignal.bdf" "inst1" { Schematic "G:/study/code/eda/sinsignal.bdf" { { -96 -40 112 0 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "dataa addcon.vhd(25) " "Warning (10492): VHDL Process Statement warning at addcon.vhd(25): signal \"dataa\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "addcon.vhd" "" { Text "G:/study/code/eda/addcon.vhd" 25 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "key_delay key_delay:inst18 " "Info: Elaborating entity \"key_delay\" for hierarchy \"key_delay:inst18\"" {  } { { "sinsignal.bdf" "inst18" { Schematic "G:/study/code/eda/sinsignal.bdf" { { 24 0 96 120 "inst18" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "key key_delay.vhd(20) " "Warning (10492): VHDL Process Statement warning at key_delay.vhd(20): signal \"key\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "key_delay.vhd" "" { Text "G:/study/code/eda/key_delay.vhd" 20 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div40 div40:inst16 " "Info: Elaborating entity \"div40\" for hierarchy \"div40:inst16\"" {  } { { "sinsignal.bdf" "inst16" { Schematic "G:/study/code/eda/sinsignal.bdf" { { 280 768 864 376 "inst16" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div1000 div1000:inst6 " "Info: Elaborating entity \"div1000\" for hierarchy \"div1000:inst6\"" {  } { { "sinsignal.bdf" "inst6" { Schematic "G:/study/code/eda/sinsignal.bdf" { { 280 624 720 376 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div10 div10:inst12 " "Info: Elaborating entity \"div10\" for hierarchy \"div10:inst12\"" {  } { { "sinsignal.bdf" "inst12" { Schematic "G:/study/code/eda/sinsignal.bdf" { { 280 480 576 376 "inst12" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FM FM:inst5 " "Info: Elaborating entity \"FM\" for hierarchy \"FM:inst5\"" {  } { { "sinsignal.bdf" "inst5" { Schematic "G:/study/code/eda/sinsignal.bdf" { { 104 216 384 200 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}