sinsignal.map.qmsg

来自「fpga的应用」· QMSG 代码 · 共 138 行 · 第 1/5 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Sep 24 11:37:29 2007 " "Info: Processing started: Mon Sep 24 11:37:29 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sinsignal -c sinsignal " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sinsignal -c sinsignal" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cnt1000.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file cnt1000.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cnt1000-behav " "Info: Found design unit 1: cnt1000-behav" {  } { { "cnt1000.vhd" "" { Text "G:/study/code/eda/cnt1000.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 cnt1000 " "Info: Found entity 1: cnt1000" {  } { { "cnt1000.vhd" "" { Text "G:/study/code/eda/cnt1000.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sinsignal.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file sinsignal.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 sinsignal " "Info: Found entity 1: sinsignal" {  } { { "sinsignal.bdf" "" { Schematic "G:/study/code/eda/sinsignal.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mysin_st.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file mysin_st.v" { { "Info" "ISGN_ENTITY_NAME" "1 mysin_st " "Info: Found entity 1: mysin_st" {  } { { "mysin_st.v" "" { Text "G:/study/code/eda/mysin_st.v" 23 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mysin.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file mysin.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mysin-SYN " "Info: Found design unit 1: mysin-SYN" {  } { { "mysin.vhd" "" { Text "G:/study/code/eda/mysin.vhd" 47 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 mysin " "Info: Found entity 1: mysin" {  } { { "mysin.vhd" "" { Text "G:/study/code/eda/mysin.vhd" 35 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ASK.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ASK.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ASK-behav " "Info: Found design unit 1: ASK-behav" {  } { { "ASK.vhd" "" { Text "G:/study/code/eda/ASK.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ASK " "Info: Found entity 1: ASK" {  } { { "ASK.vhd" "" { Text "G:/study/code/eda/ASK.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "PSK.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file PSK.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 PSK-behav " "Info: Found design unit 1: PSK-behav" {  } { { "PSK.vhd" "" { Text "G:/study/code/eda/PSK.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 PSK " "Info: Found entity 1: PSK" {  } { { "PSK.vhd" "" { Text "G:/study/code/eda/PSK.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "div10.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file div10.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 div10-behav " "Info: Found design unit 1: div10-behav" {  } { { "div10.vhd" "" { Text "G:/study/code/eda/div10.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 div10 " "Info: Found entity 1: div10" {  } { { "div10.vhd" "" { Text "G:/study/code/eda/div10.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cnn.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file cnn.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cnn-aa " "Info: Found design unit 1: cnn-aa" {  } { { "cnn.vhd" "" { Text "G:/study/code/eda/cnn.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 cnn " "Info: Found entity 1: cnn" {  } { { "cnn.vhd" "" { Text "G:/study/code/eda/cnn.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "key_delay.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file key_delay.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 key_delay-behav " "Info: Found design unit 1: key_delay-behav" {  } { { "key_delay.vhd" "" { Text "G:/study/code/eda/key_delay.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 key_delay " "Info: Found entity 1: key_delay" {  } { { "key_delay.vhd" "" { Text "G:/study/code/eda/key_delay.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "div1000.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file div1000.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 div1000-behav " "Info: Found design unit 1: div1000-behav" {  } { { "div1000.vhd" "" { Text "G:/study/code/eda/div1000.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 div1000 " "Info: Found entity 1: div1000" {  } { { "div1000.vhd" "" { Text "G:/study/code/eda/div1000.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "div40.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file div40.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 div40-behav " "Info: Found design unit 1: div40-behav" {  } { { "div40.vhd" "" { Text "G:/study/code/eda/div40.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 div40 " "Info: Found entity 1: div40" {  } { { "div40.vhd" "" { Text "G:/study/code/eda/div40.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FM.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file FM.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 FM " "Info: Found entity 1: FM" {  } { { "FM.bdf" "" { Schematic "G:/study/code/eda/FM.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cnt10.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file cnt10.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cnt10-behav " "Info: Found design unit 1: cnt10-behav" {  } { { "cnt10.vhd" "" { Text "G:/study/code/eda/cnt10.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 cnt10 " "Info: Found entity 1: cnt10" {  } { { "cnt10.vhd" "" { Text "G:/study/code/eda/cnt10.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AM.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file AM.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 AM " "Info: Found entity 1: AM" {  } { { "AM.bdf" "" { Schematic "G:/study/code/eda/AM.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "addcon.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file addcon.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 addcon-behav " "Info: Found design unit 1: addcon-behav" {  } { { "addcon.vhd" "" { Text "G:/study/code/eda/addcon.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 addcon " "Info: Found entity 1: addcon" {  } { { "addcon.vhd" "" { Text "G:/study/code/eda/addcon.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "andd.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file andd.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 andd-andd " "Info: Found design unit 1: andd-andd" {  } { { "andd.vhd" "" { Text "G:/study/code/eda/andd.vhd" 7 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 andd " "Info: Found entity 1: andd" {  } { { "andd.vhd" "" { Text "G:/study/code/eda/andd.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "div200.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file div200.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 div200-behav " "Info: Found design unit 1: div200-behav" {  } { { "div200.vhd" "" { Text "G:/study/code/eda/div200.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 div200 " "Info: Found entity 1: div200" {  } { { "div200.vhd" "" { Text "G:/study/code/eda/div200.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "PSK_ASK.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file PSK_ASK.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 PSK_ASK " "Info: Found entity 1: PSK_ASK" {  } { { "PSK_ASK.bdf" "" { Schematic "G:/study/code/eda/PSK_ASK.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "sinsignal " "Info: Elaborating entity \"sinsignal\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mysin mysin:inst10 " "Info: Elaborating entity \"mysin\" for hierarchy \"mysin:inst10\"" {  } { { "sinsignal.bdf" "inst10" { Schematic "G:/study/code/eda/sinsignal.bdf" { { -288 64 268 -160 "inst10" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mysin_st mysin:inst10\|mysin_st:mysin_st_inst " "Info: Elaborating entity \"mysin_st\" for hierarchy \"mysin:inst10\|mysin_st:mysin_st_inst\"" {  } { { "mysin.vhd" "mysin_st_inst" { Text "G:/study/code/eda/mysin.vhd" 69 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "aprf mysin_st.v(28) " "Warning (10036): Verilog HDL or VHDL warning at mysin_st.v(28): object \"aprf\" assigned a value but never read" {  } { { "mysin_st.v" "" { Text "G:/study/code/eda/mysin_st.v" 28 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "aprp mysin_st.v(29) " "Warning (10036): Verilog HDL or VHDL warning at mysin_st.v(29): object \"aprp\" assigned a value but never read" {  } { { "mysin_st.v" "" { Text "G:/study/code/eda/mysin_st.v" 29 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "mxnb mysin_st.v(35) " "Warning (10036): Verilog HDL or VHDL warning at mysin_st.v(35): object \"mxnb\" assigned a value but never read" {  } { { "mysin_st.v" "" { Text "G:/study/code/eda/mysin_st.v" 35 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "log2nc mysin_st.v(39) " "Warning (10036): Verilog HDL or VHDL warning at mysin_st.v(39): object \"log2nc\" assigned a value but never read" {  } { { "mysin_st.v" "" { Text "G:/study/code/eda/mysin_st.v" 39 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}