sinsignal.fit.qmsg

来自「fpga的应用」· QMSG 代码 · 共 49 行 · 第 1/5 页

{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:41 " "Info: Fitter placement operations ending: elapsed time is 00:00:41" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "0.862 ns register register " "Info: Estimated most critical path is register to register delay of 0.862 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns addcon:inst1\|dataa\[4\] 1 REG LAB_X28_Y21 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X28_Y21; Fanout = 6; REG Node = 'addcon:inst1\|dataa\[4\]'" {  } { { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { addcon:inst1|dataa[4] } "NODE_NAME" } } { "addcon.vhd" "" { Text "G:/study/code/eda/addcon.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.778 ns) + CELL(0.084 ns) 0.862 ns addcon:inst1\|dataout\[4\] 2 REG LAB_X27_Y21 2 " "Info: 2: + IC(0.778 ns) + CELL(0.084 ns) = 0.862 ns; Loc. = LAB_X27_Y21; Fanout = 2; REG Node = 'addcon:inst1\|dataout\[4\]'" {  } { { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.862 ns" { addcon:inst1|dataa[4] addcon:inst1|dataout[4] } "NODE_NAME" } } { "addcon.vhd" "" { Text "G:/study/code/eda/addcon.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.084 ns ( 9.74 % ) " "Info: Total cell delay = 0.084 ns ( 9.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.778 ns ( 90.26 % ) " "Info: Total interconnect delay = 0.778 ns ( 90.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.862 ns" { addcon:inst1|dataa[4] addcon:inst1|dataout[4] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "2 7 " "Info: Average interconnect usage is 2% of the available device resources. Peak interconnect usage is 7%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x22_y12 x32_y23 " "Info: The peak interconnect region extends from location x22_y12 to location x32_y23" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:09 " "Info: Fitter routing operations ending: elapsed time is 00:00:09" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_NOT_USED" "" "Info: The Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and routability requirements required full optimization." {  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and routability requirements required full optimization." 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "25 " "Warning: Found 25 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ready 0 " "Info: Pin \"ready\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing ana