sinsignal.fit.qmsg

来自「fpga的应用」· QMSG 代码 · 共 49 行 · 第 1/5 页

{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "AM:inst17\|key_delay:inst1\|keyout~22  " "Info: Automatically promoted node AM:inst17\|key_delay:inst1\|keyout~22 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0}  } { { "key_delay.vhd" "" { Text "G:/study/code/eda/key_delay.vhd" 6 -1 0 } } { "d:/tools/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/tools/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "AM:inst17\|key_delay:inst1\|keyout~22" } } } } { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { AM:inst17|key_delay:inst1|keyout~22 } "NODE_NAME" } } { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { AM:inst17|key_delay:inst1|keyout~22 } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "div40:inst16\|clkout  " "Info: Automatically promoted node div40:inst16\|clkout " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0}  } { { "div40.vhd" "" { Text "G:/study/code/eda/div40.vhd" 6 -1 0 } } { "d:/tools/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/tools/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "div40:inst16\|clkout" } } } } { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { div40:inst16|clkout } "NODE_NAME" } } { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { div40:inst16|clkout } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_signaltap:auto_signaltap_0\|reset_all  " "Info: Automatically promoted node sld_signaltap:auto_signaltap_0\|reset_all " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset " "Info: Destination node sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset" {  } { { "d:/tools/altera/quartus60/libraries/megafunctions/sld_acquisition_buffer.vhd" "" { Text "d:/tools/altera/quartus60/libraries/megafunctions/sld_acquisition_buffer.vhd" 417 -1 0 } } { "d:/tools/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/tools/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset" } } } } { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset } "NODE_NAME" } } { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0}  } { { "d:/tools/altera/quartus60/libraries/megafunctions/sld_signaltap.vhd" "" { Text "d:/tools/altera/quartus60/libraries/megafunctions/sld_signaltap.vhd" 426 -1 0 } } { "d:/tools/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/tools/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|reset_all" } } } } { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|reset_all } "NODE_NAME" } } { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|reset_all } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:sld_hub_inst\|CLR_SIGNAL  " "Info: Automatically promoted node sld_hub:sld_hub_inst\|CLR_SIGNAL " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_signaltap:auto_signaltap_0\|reset_all " "Info: Destination node sld_signaltap:auto_signaltap_0\|reset_all" {  } { { "d:/tools/altera/quartus60/libraries/megafunctions/sld_signaltap.vhd" "" { Text "d:/tools/altera/quartus60/libraries/megafunctions/sld_signaltap.vhd" 426 -1 0 } } { "d:/tools/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/tools/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|reset_all" } } } } { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|reset_all } "NODE_NAME" } } { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|reset_all } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|gen_non_zero_sample_depth~0 " "Info: Destination node sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|gen_non_zero_sample_depth~0" {  } { { "d:/tools/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/tools/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|gen_non_zero_sample_depth~0" } } } } { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|gen_non_zero_sample_depth~0 } "NODE_NAME" } } { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|gen_non_zero_sample_depth~0 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0}  } { { "d:/tools/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/tools/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 316 -1 0 } } { "d:/tools/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/tools/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|CLR_SIGNAL" } } } } { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|CLR_SIGNAL } "NODE_NAME" } } { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|CLR_SIGNAL } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]  " "Info: Automatically promoted node sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~437 " "Info: Destination node sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~437" {  } { { "d:/tools/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/tools/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 1135 -1 0 } } { "d:/tools/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/tools/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~437" } } } } { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~437 } "NODE_NAME" } } { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~437 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~5 " "Info: Destination node sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~5" {  } { { "d:/tools/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/tools/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 1135 -1 0 } } { "d:/tools/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/tools/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~5" } } } } { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~5 } "NODE_NAME" } } { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~5 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0}  } { { "d:/tools/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/tools/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 1150 -1 0 } } { "d:/tools/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/tools/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]" } } } } { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] } "NODE_NAME" } } { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|gen_non_zero_sample_depth~0  " "Info: Automatically promoted node sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|gen_non_zero_sample_depth~0 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0}  } { { "d:/tools/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/tools/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|gen_non_zero_sample_depth~0" } } } } { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|gen_non_zero_sample_depth~0 } "NODE_NAME" } } { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|gen_non_zero_sample_depth~0 } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0}