sinsignal.tan.qmsg

来自「fpga的应用」· QMSG 代码 · 共 10 行 · 第 1/5 页

{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0 0 "Found timing assignments -- calculating delays" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "altpll1:inst\|altpll:altpll_component\|_clk0 register addcon:inst1\|dataa\[1\] register addcon:inst1\|dataout\[1\] -1.391 ns " "Info: Slack time is -1.391 ns for clock \"altpll1:inst\|altpll:altpll_component\|_clk0\" between source register \"addcon:inst1\|dataa\[1\]\" and destination register \"addcon:inst1\|dataout\[1\]\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.511 ns + Largest register register " "Info: + Largest register to register requirement is -0.511 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "10.000 ns + " "Info: + Setup relationship between source and destination is 10.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 17.642 ns " "Info: + Latch edge is 17.642 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination altpll1:inst\|altpll:altpll_component\|_clk0 10.000 ns -2.358 ns  50 " "Info: Clock period of Destination clock \"altpll1:inst\|altpll:altpll_component\|_clk0\" is 10.000 ns with  offset of -2.358 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 7.642 ns " "Info: - Launch edge is 7.642 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source altpll1:inst\|altpll:altpll_component\|_clk1 100.000 ns -2.358 ns  50 " "Info: Clock period of Source clock \"altpll1:inst\|altpll:altpll_component\|_clk1\" is 100.000 ns with  offset of -2.358 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-10.297 ns + Largest " "Info: + Largest clock skew is -10.297 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll1:inst\|altpll:altpll_component\|_clk0 destination 2.665 ns + Shortest register " "Info: + Shortest clock path from clock \"altpll1:inst\|altpll:altpll_component\|_clk0\" to destination register is 2.665 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll1:inst\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll1:inst\|altpll:altpll_component\|_clk0'" {  } { { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altpll1:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/tools/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns altpll1:inst\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 926 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 926; COMB Node = 'altpll1:inst\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.091 ns" { altpll1:inst|altpll:altpll_component|_clk0 altpll1:inst|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/tools/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.037 ns) + CELL(0.537 ns) 2.665 ns addcon:inst1\|dataout\[1\] 3 REG LCFF_X27_Y21_N3 2 " "Info: 3: + IC(1.037 ns) + CELL(0.537 ns) = 2.665 ns; Loc. = LCFF_X27_Y21_N3; Fanout = 2; REG Node = 'addcon:inst1\|dataout\[1\]'" {  } { { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.574 ns" { altpll1:inst|altpll:altpll_component|_clk0~clkctrl addcon:inst1|dataout[1] } "NODE_NAME" } } { "addcon.vhd" "" { Text "G:/study/code/eda/addcon.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.15 % ) " "Info: Total cell delay = 0.537 ns ( 20.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.128 ns ( 79.85 % ) " "Info: Total interconnect delay = 2.128 ns ( 79.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.665 ns" { altpll1:inst|altpll:altpll_component|_clk0 altpll1:inst|altpll:altpll_component|_clk0~clkctrl addcon:inst1|dataout[1] } "NODE_NAME" } } { "d:/tools/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/altera/quartus60/win/Technology_Viewer.qrui" "2.665 ns" { altpll1:inst|altpll:altpll_component|_clk0 altpll1:inst|altpll:altpll_component|_clk0~clkctrl addcon:inst1|dataout[1] } { 0.000ns 1.091ns 1.037ns } { 0.000ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll1:inst\|altpll:altpll_component\|_clk1 source 12.962 ns - Longest register " "Info: - Longest clock path from clock \"altpll1:inst\|altpll:altpll_component\|_clk1\" to source register is 12.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll1:inst\|altpll:altpll_component\|_clk1 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll1:inst\|altpll:altpll_component\|_clk1'" {  } { { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altpll1:inst|altpll:altpll_component|_clk1 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/tools/altera/quartus60/libraries/megafunctions/altpll.tdf" 764 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns altpll1:inst\|altpll:altpll_component\|_clk1~clkctrl 2 COMB CLKCTRL_G2 5 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'altpll1:inst\|altpll:altpll_component\|_clk1~clkctrl'" {  } { { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.091 ns" { altpll1:inst|altpll:altpll_component|_clk1 altpll1:inst|altpll:altpll_component|_clk1~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/tools/altera/quartus60/libraries/megafunctions/altpll.tdf" 764 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.036 ns) + CELL(0.787 ns) 2.914 ns div10:inst12\|clkout 3 REG LCFF_X64_Y19_N15 1 " "Info: 3: + IC(1.036 ns) + CELL(0.787 ns) = 2.914 ns; Loc. = LCFF_X64_Y19_N15; Fanout = 1; REG Node = 'div10:inst12\|clkout'" {  } { { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.823 ns" { altpll1:inst|altpll:altpll_component|_clk1~clkctrl div10:inst12|clkout } "NODE_NAME" } } { "div10.vhd" "" { Text "G:/study/code/eda/div10.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.583 ns) + CELL(0.000 ns) 3.497 ns div10:inst12\|clkout~clkctrl 4 COMB CLKCTRL_G5 924 " "Info: 4: + IC(0.583 ns) + CELL(0.000 ns) = 3.497 ns; Loc. = CLKCTRL_G5; Fanout = 924; COMB Node = 'div10:inst12\|clkout~clkctrl'" {  } { { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.583 ns" { div10:inst12|clkout div10:inst12|clkout~clkctrl } "NODE_NAME" } } { "div10.vhd" "" { Text "G:/study/code/eda/div10.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.023 ns) + CELL(0.787 ns) 5.307 ns div1000:inst6\|clkout 5 REG LCFF_X64_Y19_N31 1 " "Info: 5: + IC(1.023 ns) + CELL(0.787 ns) = 5.307 ns; Loc. = LCFF_X64_Y19_N31; Fanout = 1; REG Node = 'div1000:inst6\|clkout'" {  } { { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.810 ns" { div10:inst12|clkout~clkctrl div1000:inst6|clkout } "NODE_NAME" } } { "div1000.vhd" "" { Text "G:/study/code/eda/div1000.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.583 ns) + CELL(0.000 ns) 5.890 ns div1000:inst6\|clkout~clkctrl 6 COMB CLKCTRL_G6 8 " "Info: 6: + IC(0.583 ns) + CELL(0.000 ns) = 5.890 ns; Loc. = CLKCTRL_G6; Fanout = 8; COMB Node = 'div1000:inst6\|clkout~clkctrl'" {  } { { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.583 ns" { div1000:inst6|clkout div1000:inst6|clkout~clkctrl } "NODE_NAME" } } { "div1000.vhd" "" { Text "G:/study/code/eda/div1000.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.011 ns) + CELL(0.787 ns) 7.688 ns div40:inst16\|clkout 7 REG LCFF_X34_Y1_N27 1 " "Info: 7: + IC(1.011 ns) + CELL(0.787 ns) = 7.688 ns; Loc. = LCFF_X34_Y1_N27; Fanout = 1; REG Node = 'div40:inst16\|clkout'" {  } { { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.798 ns" { div1000:inst6|clkout~clkctrl div40:inst16|clkout } "NODE_NAME" } } { "div40.vhd" "" { Text "G:/study/code/eda/div40.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.737 ns) + CELL(0.000 ns) 8.425 ns div40:inst16\|clkout~clkctrl 8 COMB CLKCTRL_G13 4 " "Info: 8: + IC(0.737 ns) + CELL(0.000 ns) = 8.425 ns; Loc. = CLKCTRL_G13; Fanout = 4; COMB Node = 'div40:inst16\|clkout~clkctrl'" {  } { { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.737 ns" { div40:inst16|clkout div40:inst16|clkout~clkctrl } "NODE_NAME" } } { "div40.vhd" "" { Text "G:/study/code/eda/div40.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.051 ns) + CELL(0.787 ns) 10.263 ns key_delay:inst18\|res0 9 REG LCFF_X31_Y35_N27 2 " "Info: 9: + IC(1.051 ns) + CELL(0.787 ns) = 10.263 ns; Loc. = LCFF_X31_Y35_N27; Fanout = 2; REG Node = 'key_delay:inst18\|res0'" {  } { { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.838 ns" { div40:inst16|clkout~clkctrl key_delay:inst18|res0 } "NODE_NAME" } } { "key_delay.vhd" "" { Text "G:/study/code/eda/key_delay.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.306 ns) + CELL(0.150 ns) 10.719 ns key_delay:inst18\|keyout~22 10 COMB LCCOMB_X31_Y35_N0 1 " "Info: 10: + IC(0.306 ns) + CELL(0.150 ns) = 10.719 ns; Loc. = LCCOMB_X31_Y35_N0; Fanout = 1; COMB Node = 'key_delay:inst18\|keyout~22'" {  } { { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.456 ns" { key_delay:inst18|res0 key_delay:inst18|keyout~22 } "NODE_NAME" } } { "key_delay.vhd" "" { Text "G:/study/code/eda/key_delay.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.677 ns) + CELL(0.000 ns) 11.396 ns key_delay:inst18\|keyout~22clkctrl 11 COMB CLKCTRL_G8 29 " "Info: 11: + IC(0.677 ns) + CELL(0.000 ns) = 11.396 ns; Loc. = CLKCTRL_G8; Fanout = 29; COMB Node = 'key_delay:inst18\|keyout~22clkctrl'" {  } { { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.677 ns" { key_delay:inst18|keyout~22 key_delay:inst18|keyout~22clkctrl } "NODE_NAME" } } { "key_delay.vhd" "" { Text "G:/study/code/eda/key_delay.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.029 ns) + CELL(0.537 ns) 12.962 ns addcon:inst1\|dataa\[1\] 12 REG LCFF_X28_Y21_N9 6 " "Info: 12: + IC(1.029 ns) + CELL(0.537 ns) = 12.962 ns; Loc. = LCFF_X28_Y21_N9; Fanout = 6; REG Node = 'addcon:inst1\|dataa\[1\]'" {  } { { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.566 ns" { key_delay:inst18|keyout~22clkctrl addcon:inst1|dataa[1] } "NODE_NAME" } } { "addcon.vhd" "" { Text "G:/study/code/eda/addcon.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.835 ns ( 29.59 % ) " "Info: Total cell delay = 3.835 ns ( 29.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.127 ns ( 70.41 % ) " "Info: Total interconnect delay = 9.127 ns ( 70.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.962 ns" { altpll1:inst|altpll:altpll_component|_clk1 altpll1:inst|altpll:altpll_component|_clk1~clkctrl div10:inst12|clkout div10:inst12|clkout~clkctrl div1000:inst6|clkout div1000:inst6|clkout~clkctrl div40:inst16|clkout div40:inst16|clkout~clkctrl key_delay:inst18|res0 key_delay:inst18|keyout~22 key_delay:inst18|keyout~22clkctrl addcon:inst1|dataa[1] } "NODE_NAME" } } { "d:/tools/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/altera/quartus60/win/Technology_Viewer.qrui" "12.962 ns" { altpll1:inst|altpll:altpll_component|_clk1 altpll1:inst|altpll:altpll_component|_clk1~clkctrl div10:inst12|clkout div10:inst12|clkout~clkctrl div1000:inst6|clkout div1000:inst6|clkout~clkctrl div40:inst16|clkout div40:inst16|clkout~clkctrl key_delay:inst18|res0 key_delay:inst18|keyout~22 key_delay:inst18|keyout~22clkctrl addcon:inst1|dataa[1] } { 0.000ns 1.091ns 1.036ns 0.583ns 1.023ns 0.583ns 1.011ns 0.737ns 1.051ns 0.306ns 0.677ns 1.029ns } { 0.000ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.787ns 0.150ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.665 ns" { altpll1:inst|altpll:altpll_component|_clk0 altpll1:inst|altpll:altpll_component|_clk0~clkctrl addcon:inst1|dataout[1] } "NODE_NAME" } } { "d:/tools/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/altera/quartus60/win/Technology_Viewer.qrui" "2.665 ns" { altpll1:inst|altpll:altpll_component|_clk0 altpll1:inst|altpll:altpll_component|_clk0~clkctrl addcon:inst1|dataout[1] } { 0.000ns 1.091ns 1.037ns } { 0.000ns 0.000ns 0.537ns } } } { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.962 ns" { altpll1:inst|altpll:altpll_component|_clk1 altpll1:inst|altpll:altpll_component|_clk1~clkctrl div10:inst12|clkout div10:inst12|clkout~clkctrl div1000:inst6|clkout div1000:inst6|clkout~clkctrl div40:inst16|clkout div40:inst16|clkout~clkctrl key_delay:inst18|res0 key_delay:inst18|keyout~22 key_delay:inst18|keyout~22clkctrl addcon:inst1|dataa[1] } "NODE_NAME" } } { "d:/tools/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/altera/quartus60/win/Technology_Viewer.qrui" "12.962 ns" { altpll1:inst|altpll:altpll_component|_clk1 altpll1:inst|altpll:altpll_component|_clk1~clkctrl div10:inst12|clkout div10:inst12|clkout~clkctrl div1000:inst6|clkout div1000:inst6|clkout~clkctrl div40:inst16|clkout div40:inst16|clkout~clkctrl key_delay:inst18|res0 key_delay:inst18|keyout~22 key_delay:inst18|keyout~22clkctrl addcon:inst1|dataa[1] } { 0.000ns 1.091ns 1.036ns 0.583ns 1.023ns 0.583ns 1.011ns 0.737ns 1.051ns 0.306ns 0.677ns 1.029ns } { 0.000ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.787ns 0.150ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" {  } { { "addcon.vhd" "" { Text "G:/study/code/eda/addcon.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns - " "Info: - Micro setup delay of destination is -0.036 ns" {  } { { "addcon.vhd" "" { Text "G:/study/code/eda/addcon.vhd" 29 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.665 ns" { altpll1:inst|altpll:altpll_component|_clk0 altpll1:inst|altpll:altpll_component|_clk0~clkctrl addcon:inst1|dataout[1] } "NODE_NAME" } } { "d:/tools/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/altera/quartus60/win/Technology_Viewer.qrui" "2.665 ns" { altpll1:inst|altpll:altpll_component|_clk0 altpll1:inst|altpll:altpll_component|_clk0~clkctrl addcon:inst1|dataout[1] } { 0.000ns 1.091ns 1.037ns } { 0.000ns 0.000ns 0.537ns } } } { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.962 ns" { altpll1:inst|altpll:altpll_component|_clk1 altpll1:inst|altpll:altpll_component|_clk1~clkctrl div10:inst12|clkout div10:inst12|clkout~clkctrl div1000:inst6|clkout div1000:inst6|clkout~clkctrl div40:inst16|clkout div40:inst16|clkout~clkctrl key_delay:inst18|res0 key_delay:inst18|keyout~22 key_delay:inst18|keyout~22clkctrl addcon:inst1|dataa[1] } "NODE_NAME" } } { "d:/tools/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/altera/quartus60/win/Technology_Viewer.qrui" "12.962 ns" { altpll1:inst|altpll:altpll_component|_clk1 altpll1:inst|altpll:altpll_component|_clk1~clkctrl div10:inst12|clkout div10:inst12|clkout~clkctrl div1000:inst6|clkout div1000:inst6|clkout~clkctrl div40:inst16|clkout div40:inst16|clkout~clkctrl key_delay:inst18|res0 key_delay:inst18|keyout~22 key_delay:inst18|keyout~22clkctrl addcon:inst1|dataa[1] } { 0.000ns 1.091ns 1.036ns 0.583ns 1.023ns 0.583ns 1.011ns 0.737ns 1.051ns 0.306ns 0.677ns 1.029ns } { 0.000ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.787ns 0.150ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.880 ns - Longest register register " "Info: - Longest register to register delay is 0.880 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns addcon:inst1\|dataa\[1\] 1 REG LCFF_X28_Y21_N9 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X28_Y21_N9; Fanout = 6; REG Node = 'addcon:inst1\|dataa\[1\]'" {  } { { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { addcon:inst1|dataa[1] } "NODE_NAME" } } { "addcon.vhd" "" { Text "G:/study/code/eda/addcon.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.514 ns) + CELL(0.366 ns) 0.880 ns addcon:inst1\|dataout\[1\] 2 REG LCFF_X27_Y21_N3 2 " "Info: 2: + IC(0.514 ns) + CELL(0.366 ns) = 0.880 ns; Loc. = LCFF_X27_Y21_N3; Fanout = 2; REG Node = 'addcon:inst1\|dataout\[1\]'" {  } { { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.880 ns" { addcon:inst1|dataa[1] addcon:inst1|dataout[1] } "NODE_NAME" } } { "addcon.vhd" "" { Text "G:/study/code/eda/addcon.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.366 ns ( 41.59 % ) " "Info: Total cell delay = 0.366 ns ( 41.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.514 ns ( 58.41 % ) " "Info: Total interconnect delay = 0.514 ns ( 58.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.880 ns" { addcon:inst1|dataa[1] addcon:inst1|dataout[1] } "NODE_NAME" } } { "d:/tools/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/altera/quartus60/win/Technology_Viewer.qrui" "0.880 ns" { addcon:inst1|dataa[1] addcon:inst1|dataout[1] } { 0.000ns 0.514ns } { 0.000ns 0.366ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.665 ns" { altpll1:inst|altpll:altpll_component|_clk0 altpll1:inst|altpll:altpll_component|_clk0~clkctrl addcon:inst1|dataout[1] } "NODE_NAME" } } { "d:/tools/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/altera/quartus60/win/Technology_Viewer.qrui" "2.665 ns" { altpll1:inst|altpll:altpll_component|_clk0 altpll1:inst|altpll:altpll_component|_clk0~clkctrl addcon:inst1|dataout[1] } { 0.000ns 1.091ns 1.037ns } { 0.000ns 0.000ns 0.537ns } } } { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.962 ns" { altpll1:inst|altpll:altpll_component|_clk1 altpll1:inst|altpll:altpll_component|_clk1~clkctrl div10:inst12|clkout div10:inst12|clkout~clkctrl div1000:inst6|clkout div1000:inst6|clkout~clkctrl div40:inst16|clkout div40:inst16|clkout~clkctrl key_delay:inst18|res0 key_delay:inst18|keyout~22 key_delay:inst18|keyout~22clkctrl addcon:inst1|dataa[1] } "NODE_NAME" } } { "d:/tools/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/altera/quartus60/win/Technology_Viewer.qrui" "12.962 ns" { altpll1:inst|altpll:altpll_component|_clk1 altpll1:inst|altpll:altpll_component|_clk1~clkctrl div10:inst12|clkout div10:inst12|clkout~clkctrl div1000:inst6|clkout div1000:inst6|clkout~clkctrl div40:inst16|clkout div40:inst16|clkout~clkctrl key_delay:inst18|res0 key_delay:inst18|keyout~22 key_delay:inst18|keyout~22clkctrl addcon:inst1|dataa[1] } { 0.000ns 1.091ns 1.036ns 0.583ns 1.023ns 0.583ns 1.011ns 0.737ns 1.051ns 0.306ns 0.677ns 1.029ns } { 0.000ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.787ns 0.150ns 0.000ns 0.537ns } } } { "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.880 ns" { addcon:inst1|dataa[1] addcon:inst1|dataout[1] } "NODE_NAME" } } { "d:/tools/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/altera/quartus60/win/Technology_Viewer.qrui" "0.880 ns" { addcon:inst1|dataa[1] addcon:inst1|dataout[1] } { 0.000ns 0.514ns } { 0.000ns 0.366ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}