sinsignal.tan.qmsg

来自「fpga的应用」· QMSG 代码 · 共 10 行 · 第 1/5 页

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~UPDATEUSER " "Info: Assuming node \"altera_internal_jtag~UPDATEUSER\" is an undefined clock" {  } { { "d:/tools/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/tools/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~UPDATEUSER" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~TCKUTAP " "Info: Assuming node \"altera_internal_jtag~TCKUTAP\" is an undefined clock" {  } { { "d:/tools/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/tools/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TCKUTAP" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~CLKDRUSER " "Info: Assuming node \"altera_internal_jtag~CLKDRUSER\" is an undefined clock" {  } { { "d:/tools/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/tools/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~CLKDRUSER" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "9 " "Warning: Found 9 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "AM:inst17\|key_delay:inst1\|res0 " "Info: Detected ripple clock \"AM:inst17\|key_delay:inst1\|res0\" as buffer" {  } { { "key_delay.vhd" "" { Text "G:/study/code/eda/key_delay.vhd" 9 -1 0 } } { "d:/tools/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/tools/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "AM:inst17\|key_delay:inst1\|res0" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "AM:inst17\|key_delay:inst1\|res1 " "Info: Detected ripple clock \"AM:inst17\|key_delay:inst1\|res1\" as buffer" {  } { { "key_delay.vhd" "" { Text "G:/study/code/eda/key_delay.vhd" 9 -1 0 } } { "d:/tools/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/tools/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "AM:inst17\|key_delay:inst1\|res1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "AM:inst17\|key_delay:inst1\|keyout~22 " "Info: Detected gated clock \"AM:inst17\|key_delay:inst1\|keyout~22\" as buffer" {  } { { "key_delay.vhd" "" { Text "G:/study/code/eda/key_delay.vhd" 6 -1 0 } } { "d:/tools/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/tools/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "AM:inst17\|key_delay:inst1\|keyout~22" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "div1000:inst6\|clkout " "Info: Detected ripple clock \"div1000:inst6\|clkout\" as buffer" {  } { { "div1000.vhd" "" { Text "G:/study/code/eda/div1000.vhd" 6 -1 0 } } { "d:/tools/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/tools/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "div1000:inst6\|clkout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "div40:inst16\|clkout " "Info: Detected ripple clock \"div40:inst16\|clkout\" as buffer" {  } { { "div40.vhd" "" { Text "G:/study/code/eda/div40.vhd" 6 -1 0 } } { "d:/tools/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/tools/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "div40:inst16\|clkout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "key_delay:inst18\|res0 " "Info: Detected ripple clock \"key_delay:inst18\|res0\" as buffer" {  } { { "key_delay.vhd" "" { Text "G:/study/code/eda/key_delay.vhd" 9 -1 0 } } { "d:/tools/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/tools/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "key_delay:inst18\|res0" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "key_delay:inst18\|res1 " "Info: Detected ripple clock \"key_delay:inst18\|res1\" as buffer" {  } { { "key_delay.vhd" "" { Text "G:/study/code/eda/key_delay.vhd" 9 -1 0 } } { "d:/tools/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/tools/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "key_delay:inst18\|res1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "key_delay:inst18\|keyout~22 " "Info: Detected gated clock \"key_delay:inst18\|keyout~22\" as buffer" {  } { { "key_delay.vhd" "" { Text "G:/study/code/eda/key_delay.vhd" 6 -1 0 } } { "d:/tools/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/tools/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "key_delay:inst18\|keyout~22" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "div10:inst12\|clkout " "Info: Detected ripple clock \"div10:inst12\|clkout\" as buffer" {  } { { "div10.vhd" "" { Text "G:/study/code/eda/div10.vhd" 6 -1 0 } } { "d:/tools/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/tools/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "div10:inst12\|clkout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}