sinsignal.tan.summary

来自「fpga的应用」· SUMMARY 代码 · 共 127 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 1.270 ns
From           : sw_2
To             : sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[37]
From Clock     : --
To Clock       : clkin
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 20.589 ns
From           : AM:inst17|amsin:inst5|altsyncram:altsyncram_component|altsyncram_lr61:auto_generated|q_a[1]
To             : result[8]
From Clock     : clkin
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 9.163 ns
From           : sw_2
To             : result[8]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 8.096 ns
From           : sw_1
To             : addcon:inst1|dataa[25]
From Clock     : --
To Clock       : clkin
Failed Paths   : 0

Type           : Clock Setup: 'altpll1:inst|altpll:altpll_component|_clk0'
Slack          : -1.391 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : N/A
From           : addcon:inst1|dataa[1]
To             : addcon:inst1|dataout[1]
From Clock     : altpll1:inst|altpll:altpll_component|_clk1
To Clock       : altpll1:inst|altpll:altpll_component|_clk0
Failed Paths   : 29

Type           : Clock Setup: 'altpll1:inst|altpll:altpll_component|_clk1'
Slack          : 6.568 ns
Required Time  : 10.00 MHz ( period = 100.000 ns )
Actual Time    : N/A
From           : addcon:inst1|dataout[0]
To             : sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[20]
From Clock     : altpll1:inst|altpll:altpll_component|_clk0
To Clock       : altpll1:inst|altpll:altpll_component|_clk1
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 140.57 MHz ( period = 7.114 ns )
From           : sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[5]
To             : sld_hub:sld_hub_inst|hub_tdo
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~CLKDRUSER'
Slack          : N/A
Required Time  : None
Actual Time    : 346.62 MHz ( period = 2.885 ns )
From           : pzdyqx:nabboc|VELJ8121:JDCF0099|AJQN5180[0]
To             : pzdyqx:nabboc|VELJ8121:JDCF0099|DJFL8584[1]
From Clock     : altera_internal_jtag~CLKDRUSER
To Clock       : altera_internal_jtag~CLKDRUSER
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~UPDATEUSER'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 500.00 MHz ( period = 2.000 ns )
From           : pzdyqx:nabboc|XWDE0671[2]
To             : pzdyqx:nabboc|XWDE0671[1]
From Clock     : altera_internal_jtag~UPDATEUSER
To Clock       : altera_internal_jtag~UPDATEUSER
Failed Paths   : 0

Type           : Clock Hold: 'altpll1:inst|altpll:altpll_component|_clk1'
Slack          : -1.634 ns
Required Time  : 10.00 MHz ( period = 100.000 ns )
Actual Time    : N/A
From           : mysin:inst10|mysin_st:mysin_st_inst|asj_nco_mob_rw:ux122|data_out[7]~_Duplicate_1
To             : sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[41]
From Clock     : altpll1:inst|altpll:altpll_component|_clk0
To Clock       : altpll1:inst|altpll:altpll_component|_clk1
Failed Paths   : 43

Type           : Clock Hold: 'altpll1:inst|altpll:altpll_component|_clk0'
Slack          : 0.512 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : N/A
From           : mysin:inst10|mysin_st:mysin_st_inst|asj_dxx:ux002|dxxpdo[20]
To             : mysin:inst10|mysin_st:mysin_st_inst|segment_arr_tdl:tdl|segment_arr[0][2]
From Clock     : altpll1:inst|altpll:altpll_component|_clk0
To Clock       : altpll1:inst|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 72

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