altpll0_waveforms.html

来自「fpga的应用」· HTML 代码 · 共 14 行

HTML
14 行
字号 
<html>
<head>
<title>Sample Waveforms for altpll0.vhd </title>
</head>
<body>
<h2><CENTER>Sample behavioral waveforms for design file altpll0.vhd </CENTER></h2>
<P>The following waveforms show the behavior of altpll megafunction for the chosen set of parameters in design altpll0.vhd. The design altpll0.vhd has Cyclone II FAST pll configured in NORMAL mode The primary clock input to the PLL is INCLK0, with clock period 20000 ps. CLK0 multiply by = 2, CLK0 divide by = 1, CLK0 phase_shift = 0 CLK1 multiply by = 1, CLK1 divide by = 5, CLK1 phase_shift = 0 Input port ARESET is used. This port is active high. When asserted, it will cause the LOCKED port and all CLK outputs to drop to zero. The PLL will relock to the input clock when this port is deasserted. </P>
<CENTER><img src=altpll0_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing NORMAL mode operation. </CENTER></P>
<P><FONT size=3></P>
<P></P>
</body>
</html>

altpll0_waveforms.html - 源码说明

本页面展示了「fpga的应用」中的 altpll0_waveforms.html 源码文件，采用 HTML 编程语言编写，共 14 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

虫虫下载站收录了大量与fpga相关的技术资源，包括源代码、技术文档、电路图等，是电子工程师和嵌入式开发者的专业学习平台。

⌨️ 快捷键说明

复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?