control.vhd

fpga的应用

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity control is
  port(clk:in std_logic;
       dataout:out std_logic_vector(31 downto 0));
end control;

architecture behav of control is
signal data:integer:=42949;
begin
process(clk)
  begin
    if clk'event and clk='1' then
          dataout<=conv_std_logic_vector(data,32); 
          else dataout<=conv_std_logic_vector(data,32);
     end if;
end process;
end behav;