key_delay.vhd

fpga的应用

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity key_delay is
  port(clk,key:in std_logic;
       keyout:out std_logic);
end key_delay;
architecture behav of key_delay is
signal res0,res1:std_logic;
begin
process(clk)
  begin
	if clk'event and clk='1' then
		res1<=res0;
		res0<=key;
	end if;
end process;
process(res0,res1)
  begin
	keyout<=key and res0 and(not res1);
end process;
end behav;