div40.vhd

来自「fpga的应用」· VHDL 代码 · 共 26 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity div40 is
  port(clk:in std_logic;
       clkout:out std_logic);
end div40;
architecture behav of div40 is
signal sig:integer range 0 to 39;
signal clk1:std_logic;
begin
process(clk)
 begin
    if clk'event and clk='1' then
       if sig=39 then 
            sig<=0;
            clk1<='1';
       else
            sig<=sig+1;
            clk1<='0';
       end if;
     clkout<=clk1;
     end if;

end process;
end behav;