cnt1000.vhd

来自「fpga的应用」· VHDL 代码 · 共 27 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt1000 is
  port(clk,en:in std_logic;
       cq:out std_logic_vector(9 downto 0));
end cnt1000;

architecture behav of cnt1000 is
signal q:std_logic_vector(9 downto 0);
begin 
process(clk,en)    
 begin
    if clk'event and clk='1' then  
       if en='1' then
           if q="1111100111" then 
			  q<="0000000000";
           else q<=q+'1';
           end if;
		else q<="0000000000";
        end if;
     end if;
    cq<=q;
  end process;
end behav;