sinsignal.qsf

fpga的应用

# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		sinsignal_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C35F672C6
set_global_assignment -name TOP_LEVEL_ENTITY sinsignal
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:50:10  SEPTEMBER 18, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION 6.0
set_global_assignment -name MIF_FILE sinsignal.mif
set_global_assignment -name VHDL_FILE cnt1000.vhd
set_global_assignment -name BDF_FILE sinsignal.bdf
set_global_assignment -name VECTOR_WAVEFORM_FILE cnt1000.vwf
set_global_assignment -name VECTOR_INPUT_SOURCE "G:\\study\\code\\eda\\cnt10.vwf"
set_global_assignment -name VECTOR_WAVEFORM_FILE aa.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE aaa.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE sinsignal.vwf
set_global_assignment -name VERILOG_FILE "G:/study/code/eda/mysin_st.v"
set_global_assignment -name VHDL_FILE "G:/study/code/eda/mysin.vhd"
set_global_assignment -name USER_LIBRARIES "D:/tools/altera/megacore/nco-v2.3.1/lib;"
set_global_assignment -name VHDL_FILE ASK.vhd
set_global_assignment -name VECTOR_WAVEFORM_FILE ASK.vwf
set_global_assignment -name VHDL_FILE PSK.vhd
set_global_assignment -name VECTOR_WAVEFORM_FILE PSK.vwf
set_global_assignment -name MIF_FILE sin1k.mif
set_global_assignment -name VHDL_FILE div10.vhd
set_global_assignment -name VECTOR_WAVEFORM_FILE div10.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE control.vwf
set_location_assignment PIN_N2 -to clkin
set_global_assignment -name SIGNALTAP_FILE stp1.stp
set_global_assignment -name ENABLE_SIGNALTAP ON
set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
set_global_assignment -name VHDL_FILE cnn.vhd
set_global_assignment -name VHDL_FILE key_delay.vhd
set_global_assignment -name VHDL_FILE div1000.vhd
set_global_assignment -name VHDL_FILE div40.vhd
set_global_assignment -name MIF_FILE FM.mif
set_global_assignment -name BDF_FILE FM.bdf
set_global_assignment -name VHDL_FILE cnt10.vhd
set_global_assignment -name MIF_FILE AM.mif
set_global_assignment -name BDF_FILE AM.bdf
set_location_assignment PIN_N26 -to sw_1
set_location_assignment PIN_P25 -to sw_2
set_location_assignment PIN_AE14 -to sw_3
set_location_assignment PIN_AF14 -to sw_4
set_location_assignment PIN_AD13 -to sw_5
set_location_assignment PIN_G26 -to key0
set_location_assignment PIN_P23 -to key1
set_global_assignment -name VHDL_FILE addcon.vhd
set_global_assignment -name VECTOR_WAVEFORM_FILE addcon.vwf
set_global_assignment -name SETUP_HOLD_DETECTION ON
set_global_assignment -name VHDL_FILE andd.vhd
set_global_assignment -name VECTOR_WAVEFORM_FILE cnt10.vwf
set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF
set_global_assignment -name MIF_FILE AM2.mif
set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=536899072" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=2048" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_MEM_ADDRESS_BITS=11" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to clk1m -section_id auto_signaltap_0
set_global_assignment -name MIF_FILE AM3.mif
set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON
set_global_assignment -name VHDL_FILE div200.vhd
set_global_assignment -name BDF_FILE PSK_ASK.bdf
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BIT_CNTR_BITS=6" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to datain[0] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to datain[10] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to datain[11] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to datain[12] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to datain[13] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to datain[14] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to datain[15] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to datain[16] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to datain[17] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to datain[18] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to datain[19] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to datain[1] -section_id auto_signaltap_0