mysin_vo_msim.tcl

fpga的应用

if {[file exist [project env]] > 0} {project close}
if {[file exist "G:/study/code/eda/mysin.mpf"] == 0} {
  project new G:/study/code/eda/ mysin
} else	{
project open mysin
}
if {[file exist work] ==0} 	{
  exec vlib work
  exec vmap work work}      
vlog d:/tools/altera/quartus60//eda/sim_lib/220model.v
vlog d:/tools/altera/quartus60//eda/sim_lib/altera_mf.v
vlog d:/tools/altera/quartus60//eda/sim_lib/sgate.v
vlog mysin.vo
vlog mysin_tb.v
vsim mysin_tb
do mysin_wave.do
run 22000 ns;