sinsignal.tan.rpt

来自「fpga的应用」· RPT 代码 · 共 227 行 · 第 1/5 页

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+-----------------------------------------------------------+-----------+-----------------------------------+------------------------------------------------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------------------------------------+--------------------------------------------+--------------+
; Type                                                      ; Slack     ; Required Time                     ; Actual Time                                    ; From                                                                                        ; To                                                                        ; From Clock                                 ; To Clock                                   ; Failed Paths ;
+-----------------------------------------------------------+-----------+-----------------------------------+------------------------------------------------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------------------------------------+--------------------------------------------+--------------+
; Worst-case tsu                                            ; N/A       ; None                              ; 1.270 ns                                       ; sw_2                                                                                        ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[37]                     ; --                                         ; clkin                                      ; 0            ;
; Worst-case tco                                            ; N/A       ; None                              ; 20.589 ns                                      ; AM:inst17|amsin:inst5|altsyncram:altsyncram_component|altsyncram_lr61:auto_generated|q_a[1] ; result[8]                                                                 ; clkin                                      ; --                                         ; 0            ;
; Worst-case tpd                                            ; N/A       ; None                              ; 9.163 ns                                       ; sw_2                                                                                        ; result[8]                                                                 ; --                                         ; --                                         ; 0            ;
; Worst-case th                                             ; N/A       ; None                              ; 8.096 ns                                       ; sw_1                                                                                        ; addcon:inst1|dataa[25]                                                    ; --                                         ; clkin                                      ; 0            ;
; Clock Setup: 'altpll1:inst|altpll:altpll_component|_clk0' ; -1.391 ns ; 100.00 MHz ( period = 10.000 ns ) ; N/A                                            ; addcon:inst1|dataa[1]                                                                       ; addcon:inst1|dataout[1]                                                   ; altpll1:inst|altpll:altpll_component|_clk1 ; altpll1:inst|altpll:altpll_component|_clk0 ; 29           ;
; Clock Setup: 'altpll1:inst|altpll:altpll_component|_clk1' ; 6.568 ns  ; 10.00 MHz ( period = 100.000 ns ) ; N/A                                            ; addcon:inst1|dataout[0]                                                                     ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[20]                     ; altpll1:inst|altpll:altpll_component|_clk0 ; altpll1:inst|altpll:altpll_component|_clk1 ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP'               ; N/A       ; None                              ; 140.57 MHz ( period = 7.114 ns )               ; sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[5]                                          ; sld_hub:sld_hub_inst|hub_tdo                                              ; altera_internal_jtag~TCKUTAP               ; altera_internal_jtag~TCKUTAP               ; 0            ;
; Clock Setup: 'altera_internal_jtag~CLKDRUSER'             ; N/A       ; None                              ; 346.62 MHz ( period = 2.885 ns )               ; pzdyqx:nabboc|VELJ8121:JDCF0099|AJQN5180[0]                                                 ; pzdyqx:nabboc|VELJ8121:JDCF0099|DJFL8584[1]                               ; altera_internal_jtag~CLKDRUSER             ; altera_internal_jtag~CLKDRUSER             ; 0            ;
; Clock Setup: 'altera_internal_jtag~UPDATEUSER'            ; N/A       ; None                              ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; pzdyqx:nabboc|XWDE0671[2]                                                                   ; pzdyqx:nabboc|XWDE0671[1]                                                 ; altera_internal_jtag~UPDATEUSER            ; altera_internal_jtag~UPDATEUSER            ; 0            ;
; Clock Hold: 'altpll1:inst|altpll:altpll_component|_clk1'  ; -1.634 ns ; 10.00 MHz ( period = 100.000 ns ) ; N/A                                            ; mysin:inst10|mysin_st:mysin_st_inst|asj_nco_mob_rw:ux122|data_out[7]~_Duplicate_1           ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[41]                     ; altpll1:inst|altpll:altpll_component|_clk0 ; altpll1:inst|altpll:altpll_component|_clk1 ; 43           ;
; Clock Hold: 'altpll1:inst|altpll:altpll_component|_clk0'  ; 0.512 ns  ; 100.00 MHz ( period = 10.000 ns ) ; N/A                                            ; mysin:inst10|mysin_st:mysin_st_inst|asj_dxx:ux002|dxxpdo[20]                                ; mysin:inst10|mysin_st:mysin_st_inst|segment_arr_tdl:tdl|segment_arr[0][2] ; altpll1:inst|altpll:altpll_component|_clk0 ; altpll1:inst|altpll:altpll_component|_clk0 ; 0            ;
; Total number of failed paths                              ;           ;                                   ;                                                ;                                                                                             ;                                                                           ;                                            ;                                            ; 72           ;
+-----------------------------------------------------------+-----------+-----------------------------------+------------------------------------------------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------------------------------------+--------------------------------------------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                           ;
+-------------------------------------------------------+--------------------+------+------------------+-------------+
; Option                                                ; Setting            ; From ; To               ; Entity Name ;
+-------------------------------------------------------+--------------------+------+------------------+-------------+
; Device Name                                           ; EP2C35F672C6       ;      ;                  ;             ;
; Timing Models                                         ; Final              ;      ;                  ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;                  ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;                  ;             ;
; Number of paths to report                             ; 200                ;      ;                  ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;                  ;             ;
; Use Fast Timing Models                                ; Off                ;      ;                  ;             ;
; Report IO Paths Separately                            ; Off                ;      ;                  ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;                  ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;                  ;             ;
; Cut off read during write signal paths                ; On                 ;      ;                  ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;                  ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;                  ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;                  ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;                  ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;                  ;             ;
; Enable Clock Latency                                  ; Off                ;      ;                  ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;                  ;             ;
; Cut Timing Path                                       ; On                 ;      ; EPEO2888_0       ; MDCK2395    ;
; Cut Timing Path                                       ; On                 ;      ; EPEO2888_1       ; MDCK2395    ;
; Cut Timing Path                                       ; On                 ;      ; EPEO2888_2       ; MDCK2395    ;