📄 sinsignal.fit.rpt
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; Device ; EP2C35F672C6 ; ;
; Use smart compilation ; Off ; Off ;
; Router Timing Optimization Level ; Normal ; Normal ;
; Placement Effort Multiplier ; 1.0 ; 1.0 ;
; Router Effort Multiplier ; 1.0 ; 1.0 ;
; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing ; Off ; Off ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; Optimize Timing ; Normal compilation ; Normal compilation ;
; Optimize IOC Register Placement for Timing ; On ; On ;
; Limit to One Fitting Attempt ; Off ; Off ;
; Final Placement Optimizations ; Automatically ; Automatically ;
; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
; Fitter Initial Placement Seed ; 1 ; 1 ;
; PCI I/O ; Off ; Off ;
; Weak Pull-Up Resistor ; Off ; Off ;
; Enable Bus-Hold Circuitry ; Off ; Off ;
; Auto Global Memory Control Signals ; Off ; Off ;
; Auto Packed Registers -- Stratix II/Cyclone II ; Auto ; Auto ;
; Auto Delay Chains ; On ; On ;
; Auto Merge PLLs ; On ; On ;
; Ignore PLL Mode When Merging PLLs ; Off ; Off ;
; Fitter Effort ; Auto Fit ; Auto Fit ;
; Physical Synthesis Effort Level ; Normal ; Normal ;
; Auto Global Clock ; On ; On ;
; Auto Global Register Control Signals ; On ; On ;
; Always Enable Input Buffers ; Off ; Off ;
+------------------------------------------------+--------------------------------+--------------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Netlist Optimizations ;
+-----------------------------------------------------------------------+-----------------+------------------+---------------------+-----------+-----------------------------------------------------------------------------------------+------------------+
; Node ; Action ; Operation ; Reason ; Node Port ; Destination Node ; Destination Port ;
+-----------------------------------------------------------------------+-----------------+------------------+---------------------+-----------+-----------------------------------------------------------------------------------------+------------------+
; AM:inst17|cnt10:inst|cnt[0] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; AM:inst17|lpm_mult5:inst4|lpm_mult:lpm_mult_component|mult_p8o:auto_generated|mac_mult1 ; DATAB ;
; AM:inst17|cnt10:inst|cnt[1] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; AM:inst17|lpm_mult5:inst4|lpm_mult:lpm_mult_component|mult_p8o:auto_generated|mac_mult1 ; DATAB ;
; AM:inst17|cnt10:inst|cnt[2] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; AM:inst17|lpm_mult5:inst4|lpm_mult:lpm_mult_component|mult_p8o:auto_generated|mac_mult1 ; DATAB ;
; AM:inst17|cnt10:inst|cnt[3] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; AM:inst17|lpm_mult5:inst4|lpm_mult:lpm_mult_component|mult_p8o:auto_generated|mac_mult1 ; DATAB ;
; mysin:inst10|mysin_st:mysin_st_inst|asj_nco_mob_rw:ux122|data_out[0] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; AM:inst17|lpm_mult1:inst7|lpm_mult:lpm_mult_component|mult_fao:auto_generated|mac_mult1 ; DATAA ;
; mysin:inst10|mysin_st:mysin_st_inst|asj_nco_mob_rw:ux122|data_out[0] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; mysin:inst10|mysin_st:mysin_st_inst|asj_nco_mob_rw:ux122|data_out[0]~_Duplicate_1 ; REGOUT ;
; mysin:inst10|mysin_st:mysin_st_inst|asj_nco_mob_rw:ux122|data_out[1] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; AM:inst17|lpm_mult1:inst7|lpm_mult:lpm_mult_component|mult_fao:auto_generated|mac_mult1 ; DATAA ;
; mysin:inst10|mysin_st:mysin_st_inst|asj_nco_mob_rw:ux122|data_out[1] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; mysin:inst10|mysin_st:mysin_st_inst|asj_nco_mob_rw:ux122|data_out[1]~_Duplicate_1 ; REGOUT ;
; mysin:inst10|mysin_st:mysin_st_inst|asj_nco_mob_rw:ux122|data_out[2] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; AM:inst17|lpm_mult1:inst7|lpm_mult:lpm_mult_component|mult_fao:auto_generated|mac_mult1 ; DATAA ;
; mysin:inst10|mysin_st:mysin_st_inst|asj_nco_mob_rw:ux122|data_out[2] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; mysin:inst10|mysin_st:mysin_st_inst|asj_nco_mob_rw:ux122|data_out[2]~_Duplicate_1 ; REGOUT ;
; mysin:inst10|mysin_st:mysin_st_inst|asj_nco_mob_rw:ux122|data_out[3] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; AM:inst17|lpm_mult1:inst7|lpm_mult:lpm_mult_component|mult_fao:auto_generated|mac_mult1 ; DATAA ;
; mysin:inst10|mysin_st:mysin_st_inst|asj_nco_mob_rw:ux122|data_out[3] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; mysin:inst10|mysin_st:mysin_st_inst|asj_nco_mob_rw:ux122|data_out[3]~_Duplicate_1 ; REGOUT ;
; mysin:inst10|mysin_st:mysin_st_inst|asj_nco_mob_rw:ux122|data_out[4] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; AM:inst17|lpm_mult1:inst7|lpm_mult:lpm_mult_component|mult_fao:auto_generated|mac_mult1 ; DATAA ;
; mysin:inst10|mysin_st:mysin_st_inst|asj_nco_mob_rw:ux122|data_out[4] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; mysin:inst10|mysin_st:mysin_st_inst|asj_nco_mob_rw:ux122|data_out[4]~_Duplicate_1 ; REGOUT ;
; mysin:inst10|mysin_st:mysin_st_inst|asj_nco_mob_rw:ux122|data_out[5] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; AM:inst17|lpm_mult1:inst7|lpm_mult:lpm_mult_component|mult_fao:auto_generated|mac_mult1 ; DATAA ;
; mysin:inst10|mysin_st:mysin_st_inst|asj_nco_mob_rw:ux122|data_out[5] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; mysin:inst10|mysin_st:mysin_st_inst|asj_nco_mob_rw:ux122|data_out[5]~_Duplicate_1 ; REGOUT ;
; mysin:inst10|mysin_st:mysin_st_inst|asj_nco_mob_rw:ux122|data_out[6] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; AM:inst17|lpm_mult1:inst7|lpm_mult:lpm_mult_component|mult_fao:auto_generated|mac_mult1 ; DATAA ;
; mysin:inst10|mysin_st:mysin_st_inst|asj_nco_mob_rw:ux122|data_out[6] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; mysin:inst10|mysin_st:mysin_st_inst|asj_nco_mob_rw:ux122|data_out[6]~_Duplicate_1 ; REGOUT ;
; mysin:inst10|mysin_st:mysin_st_inst|asj_nco_mob_rw:ux122|data_out[7] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; AM:inst17|lpm_mult1:inst7|lpm_mult:lpm_mult_component|mult_fao:auto_generated|mac_mult1 ; DATAA ;
; mysin:inst10|mysin_st:mysin_st_inst|asj_nco_mob_rw:ux122|data_out[7] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; mysin:inst10|mysin_st:mysin_st_inst|asj_nco_mob_rw:ux122|data_out[7]~_Duplicate_1 ; REGOUT ;
; mysin:inst10|mysin_st:mysin_st_inst|asj_nco_mob_rw:ux122|data_out[8] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; AM:inst17|lpm_mult1:inst7|lpm_mult:lpm_mult_component|mult_fao:auto_generated|mac_mult1 ; DATAA ;
; mysin:inst10|mysin_st:mysin_st_inst|asj_nco_mob_rw:ux122|data_out[8] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; mysin:inst10|mysin_st:mysin_st_inst|asj_nco_mob_rw:ux122|data_out[8]~_Duplicate_1 ; REGOUT ;
; mysin:inst10|mysin_st:mysin_st_inst|asj_nco_mob_rw:ux122|data_out[9] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; AM:inst17|lpm_mult1:inst7|lpm_mult:lpm_mult_component|mult_fao:auto_generated|mac_mult1 ; DATAA ;
; mysin:inst10|mysin_st:mysin_st_inst|asj_nco_mob_rw:ux122|data_out[9] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; mysin:inst10|mysin_st:mysin_st_inst|asj_nco_mob_rw:ux122|data_out[9]~_Duplicate_1 ; REGOUT ;
; mysin:inst10|mysin_st:mysin_st_inst|asj_nco_mob_rw:ux122|data_out[10] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; AM:inst17|lpm_mult1:inst7|lpm_mult:lpm_mult_component|mult_fao:auto_generated|mac_mult1 ; DATAA ;
; mysin:inst10|mysin_st:mysin_st_inst|asj_nco_mob_rw:ux122|data_out[10] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; mysin:inst10|mysin_st:mysin_st_inst|asj_nco_mob_rw:ux122|data_out[10]~_Duplicate_1 ; REGOUT ;
; mysin:inst10|mysin_st:mysin_st_inst|asj_nco_mob_rw:ux122|data_out[11] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; AM:inst17|lpm_mult1:inst7|lpm_mult:lpm_mult_component|mult_fao:auto_generated|mac_mult1 ; DATAA ;
; mysin:inst10|mysin_st:mysin_st_inst|asj_nco_mob_rw:ux122|data_out[11] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; mysin:inst10|mysin_st:mysin_st_inst|asj_nco_mob_rw:ux122|data_out[11]~_Duplicate_1 ; REGOUT ;
+-----------------------------------------------------------------------+-----------------+------------------+---------------------+-----------+-----------------------------------------------------------------------------------------+------------------+
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in G:/study/code/eda/sinsignal.pin.
+----------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Usage Summary ;
+---------------------------------------------+------------------------------------------------------------------------------+
; Resource ; Usage ;
+---------------------------------------------+------------------------------------------------------------------------------+
; Total logic elements ; 1,418 / 33,216 ( 4 % ) ;
; -- Combinational with no register ; 306 ;
; -- Register only ; 396 ;
; -- Combinational with a register ; 716 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 338 ;
; -- 3 input functions ; 338 ;
; -- <=2 input functions ; 346 ;
; -- Register only ; 396 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 757 ;
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