📄 agc_v3.v
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`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08:42:19 08/08/06
// Design Name:
// Module Name: AGC
// Project Name:
// Target Device:
// Tool versions:
// Description:
// io ports:
// AGC_clk; input clock signal frequency is 5MHz
// AGC_rst: input reset signal, active low
// AGC_en: high indicate the AGC signal output enable
// seq_in_re, seq_in_im: 10bits input real and image sequence
// AGC_en: AGC output enable signal
// AGC_signal: 8bits output AGC signal
// signal_power: 32 bits output signal indicate the current signal power
//
// function:
// generate the AGC control signal and the current signal power
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module AGC_v3(AGC_clk, AGC_rst, AGC_nd, seq_in_re, seq_in_im, AGC_en,AGC_signal,
ams_n,///dsp interface
are_n,///dsp interface
aoe_n,
awe_n,
dsp_addr,
bus_in,
AGC_bus_out,
signal_power_dB, signal_power, temp_Gain, peak_detected, state_trace);
input AGC_clk;
input AGC_rst;
input AGC_nd;
input [9:0]seq_in_re, seq_in_im;
input peak_detected;
input state_trace;
input ams_n;///dsp interface
input are_n;///dsp interface
input aoe_n;
input awe_n;
input [18:0] dsp_addr;///dsp interface
input [15:0] bus_in;///dsp interface
output [15:0] AGC_bus_out;
output AGC_en;
output [7:0] AGC_signal;
output [7:0] signal_power_dB; // signal power offer for the short training sequence detection
output [25:0] signal_power;
output [9:0] temp_Gain;
wire [9:0]factor;
wire agc_reg_wr_en;
// reg [9:0] temp_Gain;
wire [25:0] signal_power;
reg [6:0] seq_count;
reg AGC_en;
reg [7:0] AGC_signal;
wire [7:0] AGC_signal_temp;
reg agc_cal_en;
wire cor_rdy;
wire [20:0]cout_re;
wire [7:0] temp_p_word;
wire [25:0] AGC_out_re, AGC_out_im;
reg [12:0]state_count;
reg [9:0] SCL_FACTOR;
assign factor = SCL_FACTOR;
assign signal_power_dB = temp_p_word;
parameter REF_Power = 8'hb0;
// AGC_signal : look up table
correlation_v2 get_signal_power (
.rst(AGC_rst),
.cor_en(AGC_nd),
.dinA_re(seq_in_re),
.dinA_im(seq_in_im),
.dinB_re(seq_in_re),
.dinB_im(seq_in_im),
.clk(AGC_clk),
.inte_out_re(signal_power),
.inte_out_im(AGC_out_im),
.rdy(cor_rdy)
);
log_table log_lu_table (
.log_data_in(signal_power[25:5]), //25:5
.log_clk(AGC_clk),
.log_cal_en(cor_rdy),
.log_res_out(temp_p_word) //2^6
);
always @(posedge AGC_clk or negedge AGC_rst)
if(~AGC_rst)
state_count <= 0;
else if(state_count == 80)
state_count <= 0;
else if(agc_cal_en)
state_count <= state_count + 1;
else
state_count <= 0;
//
always @(posedge AGC_clk or negedge AGC_rst)
if(!AGC_rst)
AGC_signal <= 8'h00;
else if(state_count == 8'd63&& AGC_nd && (!peak_detected))
if(temp_Gain[9:8] == 0)
AGC_signal <= temp_Gain[7:0];
else if(temp_Gain[9])
AGC_signal <= 0;
else
AGC_signal <= 8'hff;
else if(state_count == 8'd63 && AGC_nd && peak_detected)
if(temp_Gain[9:8] == 0)
AGC_signal <= temp_Gain[7:0];
else if(temp_Gain[9])
AGC_signal <= 0;
else
AGC_signal <= 8'hff;
else
AGC_signal <= AGC_signal;
//wire signed [8:0] diff = {1'b0, REF_Power} - {1'b0, temp_p_word};
//
//always @(posedge AGC_clk or negedge AGC_rst)
// if(~AGC_rst)
// temp_Gain <= 0;
// else if((!state_trace))
// if(temp_p_word < 8'h9a || temp_p_word > 8'hb2)
// temp_Gain <= {2'b0, AGC_signal} + {diff[8], diff[8], diff[8:1]}; // scale_factor 0.5
// else
// begin
// if(diff[8:2] == 7'h7f)
// temp_Gain <= {2'b0, AGC_signal};
// else
// temp_Gain <= {2'b0, AGC_signal} + {diff[8], diff[8], diff[8], diff[8:2]}; // scale_factor 0.25
// end
// else if(state_trace )
// if(temp_p_word < 8'h9a || temp_p_word > 8'hb2)
// temp_Gain <= {2'b0, AGC_signal} + {diff[8], diff[8], diff[8:1]}; // scale_factor 0.5
// else
// begin
// if(diff[8:3] == 6'h3f)
// temp_Gain <= {2'b0, AGC_signal};
// else
// temp_Gain <= {2'b0, AGC_signal} + {diff[8], diff[8], diff[8], diff[8], diff[8], diff[8:3]}; // scale_factor 0.125
// end
// else
// temp_Gain <= temp_Gain;
//always@(posedge clk_40M)
// if(RST==1'b0)
// wr_finish_temp<=1'b0;
// else if(wr_finish==1'b1)
// wr_finish_temp<=1'b1;
// else if(ams_n==1'b0 && awe_n==1'b0 && dsp_addr==19'h02000)
// wr_finish_temp<=bus[0];
// else
// wr_finish_temp<=wr_finish_temp;
wire scl_factor_reg_wr_en = !ams_n && !awe_n && (dsp_addr == 19'h01001);
always @(posedge AGC_clk or negedge AGC_rst)
if(~AGC_rst)
SCL_FACTOR <= 10'b00_1000_0000;
else if(scl_factor_reg_wr_en)
SCL_FACTOR <= bus_in[9:0];
else
SCL_FACTOR <= SCL_FACTOR;
wire [8:0] DIFF_REF = {1'b0, REF_Power} - {1'b0, temp_p_word}; //9bit signed Q3
wire [7:0] ERROR_SIG = SMUL_SCL(DIFF_REF, SCL_FACTOR);
assign temp_Gain = (temp_p_word < 8'hA8 || temp_p_word > 8'hb8)?{2'b0, AGC_signal} + {ERROR_SIG[7], ERROR_SIG[7], ERROR_SIG}:{2'b0, AGC_signal} + {ERROR_SIG[7], ERROR_SIG[7], ERROR_SIG[7], ERROR_SIG[7:1]};
function [7:0] SMUL_SCL;
input [8:0] A; //Q3
input [9:0] FC; //Q9
reg [8:0] ABS_A;
reg [18:0] MUL;
reg [8:0] MUL_ROUND;
reg [7:0] MUL_LIM;
reg MUL_over;
begin
if (A[8])
ABS_A = -A;
else
ABS_A = A;
MUL = ABS_A * FC;
MUL_ROUND = MUL[17:9] + MUL[8];
MUL_over = MUL_ROUND[8] | MUL_ROUND[7];
if (MUL_over)
MUL_LIM = 127;
else
MUL_LIM = MUL_ROUND[7:0];
if (A[8])
SMUL_SCL = -MUL_LIM;
else
SMUL_SCL = MUL_LIM;
end
endfunction
//temp_p_word ---> power_gain_table addr // 65 seq_count == 65
//assign temp_p_word1[5:0] = temp_p_word [7:2] - 3 ; // -(108 - 15 - 90)
always @(posedge AGC_clk or negedge AGC_rst)
if(~AGC_rst)
agc_cal_en <= 0;
else if(cor_rdy)
agc_cal_en <= 1;
else
agc_cal_en <= 0;
always @(posedge AGC_clk or negedge AGC_rst)
if(~AGC_rst)
AGC_en <= 1;
else if(state_count == 63)
AGC_en <= 0;
else
AGC_en <= 1;
endmodule
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