log_table.v

自动增益控制Verilog编程

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    09:35:42 08/19/06
// Design Name:    
// Module Name:    log_table
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//				io ports:
//				  	input log_data_in: 21bits value needed to calculate the logarithm
//				 	input log_clk:	clock signal
//					input log_cal_en:	enable signal
//					
//					output log_res_out: the 8bits logarithm of the input
//
//				function:
//					calculate the logarithm of the current input
//
//				note:
//					the output is one clock period delayed of the corresponding input value
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module log_table(log_data_in, log_clk, log_cal_en, log_res_out);
    input [20:0] log_data_in;
    input log_clk;
	 input log_cal_en;
	 output [7:0] log_res_out;	  
	 
	 reg [9:0] table_addr;
	 reg table_read_en;
	 reg [20:0] temp_addr;

// log  look up table
 log_table1024_8 log_table (
    .addr(table_addr),
    .clk(log_clk),
    .dout(log_res_out),
    .en(log_cal_en));

// generate look up table address    
	 always @(log_data_in)
	 begin
	 	 if(!log_cal_en)
		 begin
			 table_addr = 0;
			 table_read_en = 0;
			 temp_addr = 0;
		 end
		 else
		 begin 
		 	 table_read_en = 1;
		 	 if(!(|log_data_in[20:8]))		
			 begin
			 	 table_addr = {2'b00, log_data_in[7:0]};
			 	 
			 end
			 else
			 begin
				 temp_addr = log_data_in - 256;
				 if(!(|temp_addr[20:11]))
				 begin				 	 
				 	 table_addr = {2'b01, temp_addr[10:3]};
				 end
				 else
				 begin
				 	 temp_addr = log_data_in -2304;
			 
					 if(!(|temp_addr[20:14]))	
					 begin
					 	
					 	 table_addr = {3'b100, temp_addr[13:7]};
					 end		 
					 else
					 begin
					 	 temp_addr = log_data_in - 18688; //  16384  16384 + 2304 = 18688
						 if(!(|temp_addr[20:17])) 
						 begin
						 	 			
						 	 table_addr = {3'b101, temp_addr[16:10]};
						 end
						 else
						 begin
						 	 temp_addr = log_data_in - 149760; //131072  131072+16384+2304	= 149760
							 					 	 
							 table_addr = {2'b11, temp_addr[20:13]};
							 
						 end
					 end
				 end

			 end
		 end	 	
	 end	

endmodule