correlation_v2.v

自动增益控制Verilog编程

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:  
// Engineer:
//
// Create Date:    14:44:08 06/27/06
// Design Name:    
// Module Name:    correlation
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:  correlation and integrate module
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module correlation_v2(rst, cor_en, dinA_re, dinA_im, dinB_re, dinB_im, clk, inte_out_re, inte_out_im, rdy);
		input signed [9:0]dinA_re, dinA_im, dinB_re, dinB_im;
		input clk;
		input rst;	// reset signal, low level to reset the fifo			
		input cor_en;

		output [25:0]inte_out_re, inte_out_im;
		output rdy;
	
		reg signed [20:0]cout_re, cout_im;
		reg cor_rdy; 
		reg [6:0]seq_count;

integrator64 integrator_inst (
    .rst(rst), 
    .clk(clk), 
    .nd(cor_rdy), 
    .din_re(cout_re[20:1]),//20:9 
    .din_im(cout_im[20:1]), 
    .inte_out_re(inte_out_re), 
    .inte_out_im(inte_out_im),
	 .inte_rdy(rdy)
    );

		always @(posedge clk or negedge rst)
		begin
			if(!rst)
			begin
				cout_re <= 0;
				cout_im <= 0;
			end
			else
			begin
				cor_rdy <= cor_en;
				
				if(cor_en)
				begin	
			  
					cout_re <= dinA_re*dinB_re + dinA_im*dinB_im;
					cout_im <= dinA_im*dinB_re - dinA_re*dinB_im;
					
				end

			end			
		end		

endmodule