integrator64.v

自动增益控制Verilog编程

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    09:22:42 07/01/06
// Design Name:    
// Module Name:    integrator64
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module integrator64(rst, clk, nd, din_re, din_im, inte_out_re, inte_out_im, inte_rdy);
input rst;			// reset signal: active low
input clk, nd;		 // nd --> new data input: active high
input signed [19:0]din_re, din_im;	//20

output signed [25:0]inte_out_re, inte_out_im;  //26
output inte_rdy;

reg inte_rdy;
wire sub_en;
reg signed [25:0]inte_out_re, inte_out_im;
wire [5:0] data_count_re, data_count_im;
wire signed [19:0]dout_re, dout_im;
wire full_re, full_im, empty_re, empty_im;

delay64_20bit delay64_re (
    .clk(clk),
    .sinit(!rst),
    .din(din_re),
    .wr_en(nd),
    .rd_en(sub_en),
    .dout(dout_re),
    .full(full_re),
    .empty(empty_re),
    .data_count(data_count_re));

delay64_20bit delay64_im (
    .clk(clk),
    .sinit(!rst),
    .din(din_im),
    .wr_en(nd),
    .rd_en(sub_en),
    .dout(dout_im),
    .full(full_im),
    .empty(empty_im),
    .data_count(data_count_im));



and(sub_en, data_count_re[5], data_count_re[4], data_count_re[3], data_count_re[2], data_count_re[1]);

always @(posedge clk)
begin
	if(!rst)
	begin
		inte_out_re = 0;		
		inte_out_im = 0;	
		inte_rdy <= 0;
	end 
	else
	begin
		if( nd == 1 )
		begin			
			inte_out_re = inte_out_re +  din_re; //  
			inte_out_im = inte_out_im +  din_im;
			
		end
		
		if( sub_en == 1)
		begin
			inte_out_re = inte_out_re - dout_re;
			inte_out_im = inte_out_im - dout_im;
			inte_rdy <= 1;
		end				  

	end
end



endmodule