📄 count.tan.rpt
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Timing Analyzer report for count
Sat Dec 29 12:42:13 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+-------+---------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+-------+---------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 38.299 ns ; start ; show[0] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+-------+---------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C6Q240C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+----------------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+--------+---------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+--------+---------+
; N/A ; None ; 38.299 ns ; start ; show[0] ;
; N/A ; None ; 38.188 ns ; start ; show[4] ;
; N/A ; None ; 38.030 ns ; start ; show[2] ;
; N/A ; None ; 37.907 ns ; start ; show[1] ;
; N/A ; None ; 37.798 ns ; start ; show[3] ;
; N/A ; None ; 37.331 ns ; ini[1] ; show[0] ;
; N/A ; None ; 37.220 ns ; ini[1] ; show[4] ;
; N/A ; None ; 37.062 ns ; ini[1] ; show[2] ;
; N/A ; None ; 36.857 ns ; ini[2] ; show[1] ;
; N/A ; None ; 36.830 ns ; ini[1] ; show[3] ;
; N/A ; None ; 34.113 ns ; start ; show[7] ;
; N/A ; None ; 33.768 ns ; ini[2] ; show[0] ;
; N/A ; None ; 33.670 ns ; ini[2] ; show[4] ;
; N/A ; None ; 33.623 ns ; start ; show[6] ;
; N/A ; None ; 33.294 ns ; ini[3] ; show[2] ;
; N/A ; None ; 33.280 ns ; ini[2] ; show[3] ;
; N/A ; None ; 33.227 ns ; ini[3] ; show[1] ;
; N/A ; None ; 33.145 ns ; ini[1] ; show[7] ;
; N/A ; None ; 32.655 ns ; ini[1] ; show[6] ;
; N/A ; None ; 30.690 ns ; ini[4] ; show[2] ;
; N/A ; None ; 30.623 ns ; ini[4] ; show[1] ;
; N/A ; None ; 30.553 ns ; ini[4] ; show[3] ;
; N/A ; None ; 30.348 ns ; start ; show[5] ;
; N/A ; None ; 30.138 ns ; ini[3] ; show[0] ;
; N/A ; None ; 30.053 ns ; ini[3] ; show[4] ;
; N/A ; None ; 29.595 ns ; ini[2] ; show[7] ;
; N/A ; None ; 29.380 ns ; ini[1] ; show[5] ;
; N/A ; None ; 29.105 ns ; ini[2] ; show[6] ;
; N/A ; None ; 27.534 ns ; ini[4] ; show[0] ;
; N/A ; None ; 26.476 ns ; ini[5] ; show[4] ;
; N/A ; None ; 26.459 ns ; ini[5] ; show[2] ;
; N/A ; None ; 26.392 ns ; ini[5] ; show[1] ;
; N/A ; None ; 26.322 ns ; ini[5] ; show[3] ;
; N/A ; None ; 25.978 ns ; ini[3] ; show[7] ;
; N/A ; None ; 25.830 ns ; ini[2] ; show[5] ;
; N/A ; None ; 25.488 ns ; ini[3] ; show[6] ;
; N/A ; None ; 23.636 ns ; ini[6] ; show[4] ;
; N/A ; None ; 23.619 ns ; ini[6] ; show[2] ;
; N/A ; None ; 23.552 ns ; ini[6] ; show[1] ;
; N/A ; None ; 23.482 ns ; ini[6] ; show[3] ;
; N/A ; None ; 23.387 ns ; ini[4] ; show[7] ;
; N/A ; None ; 23.346 ns ; ini[6] ; show[5] ;
; N/A ; None ; 23.303 ns ; ini[5] ; show[0] ;
; N/A ; None ; 23.118 ns ; ini[7] ; show[6] ;
; N/A ; None ; 22.897 ns ; ini[4] ; show[6] ;
; N/A ; None ; 22.281 ns ; ini[6] ; show[7] ;
; N/A ; None ; 22.213 ns ; ini[3] ; show[5] ;
; N/A ; None ; 20.463 ns ; ini[6] ; show[0] ;
; N/A ; None ; 20.133 ns ; ini[7] ; show[4] ;
; N/A ; None ; 20.116 ns ; ini[7] ; show[2] ;
; N/A ; None ; 20.049 ns ; ini[7] ; show[1] ;
; N/A ; None ; 19.979 ns ; ini[7] ; show[3] ;
; N/A ; None ; 19.843 ns ; ini[7] ; show[5] ;
; N/A ; None ; 19.622 ns ; ini[4] ; show[5] ;
; N/A ; None ; 16.960 ns ; ini[7] ; show[0] ;
; N/A ; None ; 16.804 ns ; ini[0] ; show[7] ;
; N/A ; None ; 16.314 ns ; ini[0] ; show[6] ;
; N/A ; None ; 14.371 ns ; ini[5] ; show[7] ;
; N/A ; None ; 13.881 ns ; ini[5] ; show[6] ;
; N/A ; None ; 13.329 ns ; ini[0] ; show[4] ;
; N/A ; None ; 13.312 ns ; ini[0] ; show[2] ;
; N/A ; None ; 13.245 ns ; ini[0] ; show[1] ;
; N/A ; None ; 13.175 ns ; ini[0] ; show[3] ;
; N/A ; None ; 13.039 ns ; ini[0] ; show[5] ;
; N/A ; None ; 11.857 ns ; ini[4] ; show[4] ;
; N/A ; None ; 11.266 ns ; ini[1] ; show[1] ;
; N/A ; None ; 11.172 ns ; ini[2] ; show[2] ;
; N/A ; None ; 11.041 ns ; ini[6] ; show[6] ;
; N/A ; None ; 10.921 ns ; ini[7] ; show[7] ;
; N/A ; None ; 10.815 ns ; ini[3] ; show[3] ;
; N/A ; None ; 10.606 ns ; ini[5] ; show[5] ;
; N/A ; None ; 10.156 ns ; ini[0] ; show[0] ;
+-------+-------------------+-----------------+--------+---------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Sat Dec 29 12:42:13 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off count -c count --timing_analysis_only
Warning: Timing Analysis is analyzing one or more combinational loops as latches
Warning: Node "sta[0]" is a latch
Warning: Node "sta[1]" is a latch
Warning: Node "finish$latch" is a latch
Info: Found combinational loop of 32 nodes
Info: Node "num~688"
Info: Node "Equal2~111"
Info: Node "process0~2"
Info: Node "Add0~537"
Info: Node "num~695"
Info: Node "Equal2~112"
Info: Node "Add0~536COUT1_544"
Info: Node "Add0~536"
Info: Node "Add0~535"
Info: Node "num~694"
Info: Node "Add0~534COUT1_543"
Info: Node "Add0~534"
Info: Node "Add0~533"
Info: Node "num~693"
Info: Node "Add0~532"
Info: Node "Add0~531"
Info: Node "num~692"
Info: Node "Add0~530COUT1"
Info: Node "Add0~530"
Info: Node "Add0~529"
Info: Node "num~691"
Info: Node "Add0~528COUT1_542"
Info: Node "Add0~528"
Info: Node "Add0~527"
Info: Node "num~690"
Info: Node "Add0~526COUT1_541"
Info: Node "Add0~526"
Info: Node "Add0~525"
Info: Node "num~689"
Info: Node "Add0~524COUT1_540"
Info: Node "Add0~524"
Info: Node "Add0~523"
Info: Longest tpd from source pin "start" to destination pin "show[0]" is 38.299 ns
Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_205; Fanout = 3; PIN Node = 'start'
Info: 2: + IC(5.383 ns) + CELL(0.114 ns) = 6.972 ns; Loc. = LC_X26_Y19_N9; Fanout = 27; COMB Node = 'process0~133'
Info: 3: + IC(0.000 ns) + CELL(27.974 ns) = 34.946 ns; Loc. = LC_X26_Y20_N8; Fanout = 5; COMB LOOP Node = 'num~688'
Info: Loc. = LC_X26_Y20_N0; Node "Add0~523"
Info: Loc. = LC_X26_Y20_N3; Node "Add0~529"
Info: Loc. = LC_X26_Y20_N5; Node "Add0~534COUT1_543"
Info: Loc. = LC_X26_Y20_N2; Node "Add0~528COUT1_542"
Info: Loc. = LC_X25_Y20_N3; Node "num~692"
Info: Loc. = LC_X26_Y19_N8; Node "num~695"
Info: Loc. = LC_X26_Y20_N9; Node "Equal2~111"
Info: Loc. = LC_X26_Y20_N1; Node "Add0~526"
Info: Loc. = LC_X26_Y20_N4; Node "Add0~531"
Info: Loc. = LC_X26_Y20_N6; Node "Add0~536COUT1_544"
Info: Loc. = LC_X25_Y20_N4; Node "Equal2~112"
Info: Loc. = LC_X25_Y20_N6; Node "num~689"
Info: Loc. = LC_X26_Y20_N3; Node "Add0~530COUT1"
Info: Loc. = LC_X26_Y20_N5; Node "Add0~534"
Info: Loc. = LC_X26_Y20_N0; Node "Add0~524COUT1_540"
Info: Loc. = LC_X26_Y20_N1; Node "Add0~525"
Info: Loc. = LC_X26_Y20_N2; Node "Add0~528"
Info: Loc. = LC_X25_Y20_N2; Node "num~693"
Info: Loc. = LC_X26_Y20_N0; Node "Add0~524"
Info: Loc. = LC_X25_Y20_N7; Node "num~690"
Info: Loc. = LC_X26_Y20_N5; Node "Add0~533"
Info: Loc. = LC_X26_Y20_N6; Node "Add0~536"
Info: Loc. = LC_X26_Y20_N8; Node "num~688"
Info: Loc. = LC_X26_Y20_N2; Node "Add0~527"
Info: Loc. = LC_X26_Y20_N3; Node "Add0~530"
Info: Loc. = LC_X25_Y20_N5; Node "num~694"
Info: Loc. = LC_X26_Y19_N4; Node "process0~2"
Info: Loc. = LC_X26_Y20_N7; Node "Add0~537"
Info: Loc. = LC_X26_Y20_N1; Node "Add0~526COUT1_541"
Info: Loc. = LC_X25_Y20_N8; Node "num~691"
Info: Loc. = LC_X26_Y20_N6; Node "Add0~535"
Info: Loc. = LC_X26_Y20_N4; Node "Add0~532"
Info: 4: + IC(1.245 ns) + CELL(2.108 ns) = 38.299 ns; Loc. = PIN_196; Fanout = 0; PIN Node = 'show[0]'
Info: Total cell delay = 31.671 ns ( 82.69 % )
Info: Total interconnect delay = 6.628 ns ( 17.31 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 4 warnings
Info: Processing ended: Sat Dec 29 12:42:13 2007
Info: Elapsed time: 00:00:01
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