count.map.rpt

一个用VHDL写的倒计时程序

+---------------------------------------------+--------------+
; Total logic elements                        ; 29           ;
;     -- Combinational with no register       ; 29           ;
;     -- Register only                        ; 0            ;
;     -- Combinational with a register        ; 0            ;
;                                             ;              ;
; Logic element usage by number of LUT inputs ;              ;
;     -- 4 input functions                    ; 14           ;
;     -- 3 input functions                    ; 12           ;
;     -- 2 input functions                    ; 3            ;
;     -- 1 input functions                    ; 0            ;
;     -- 0 input functions                    ; 0            ;
;         -- Combinational cells for routing  ; 0            ;
;                                             ;              ;
; Logic elements by mode                      ;              ;
;     -- normal mode                          ; 22           ;
;     -- arithmetic mode                      ; 7            ;
;     -- qfbk mode                            ; 0            ;
;     -- register cascade mode                ; 0            ;
;     -- synchronous clear/load mode          ; 0            ;
;     -- asynchronous clear/load mode         ; 0            ;
;                                             ;              ;
; Total registers                             ; 0            ;
; Total logic cells in carry chains           ; 8            ;
; I/O pins                                    ; 19           ;
; Maximum fan-out node                        ; process0~133 ;
; Maximum fan-out                             ; 11           ;
; Total fan-out                               ; 107          ;
; Average fan-out                             ; 2.23         ;
+---------------------------------------------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                           ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M4Ks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |count                     ; 29 (29)     ; 0            ; 0           ; 0    ; 19   ; 0            ; 29 (29)      ; 0 (0)             ; 0 (0)            ; 8 (8)           ; 0 (0)      ; |count              ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                               ;
+----------------------------------------------------+---------------------+------------------------+
; Latch Name                                         ; Latch Enable Signal ; Free of Timing Hazards ;
+----------------------------------------------------+---------------------+------------------------+
; finish$latch                                       ; GND                 ; yes                    ;
; sta[0]                                             ; GND                 ; yes                    ;
; sta[1]                                             ; GND                 ; yes                    ;
; Number of user-specified and inferred latches = 3  ;                     ;                        ;
+----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------------+
; Logic Cells Representing Combinational Loops               ;
+--------------------------------------------------------+---+
; Logic Cell Name                                        ;   ;
+--------------------------------------------------------+---+
; show[0]~6                                              ;   ;
; show[1]~5                                              ;   ;
; show[2]~4                                              ;   ;
; show[3]~3                                              ;   ;
; show[4]~2                                              ;   ;
; show[5]~1                                              ;   ;
; show[6]~0                                              ;   ;
; Equal3~0                                               ;   ;
; Number of logic cells representing combinational loops ; 8 ;
+--------------------------------------------------------+---+
Note: All cells listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; No         ; |count|num~8               ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sat Dec 29 12:42:01 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off count -c count
Info: Found 2 design units, including 1 entities, in source file count.vhd
    Info: Found design unit 1: count-five
    Info: Found entity 1: count
Info: Elaborating entity "count" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at count.vhd(19): signal "sta" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at count.vhd(19): signal "ini" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at count.vhd(20): signal "sta" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at count.vhd(24): signal "sta" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10631): VHDL Process Statement warning at count.vhd(16): inferring latch(es) for signal or variable "num", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at count.vhd(16): inferring latch(es) for signal or variable "sta", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at count.vhd(16): inferring latch(es) for signal or variable "finish", which holds its previous value in one or more paths through the process
Info (10041): Verilog HDL or VHDL info at count.vhd(16): inferred latch for "finish"
Info (10041): Verilog HDL or VHDL info at count.vhd(16): inferred latch for "sta[0]"
Info (10041): Verilog HDL or VHDL info at count.vhd(16): inferred latch for "sta[1]"
Warning: Design contains 1 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "t1a"
Info: Implemented 48 device resources after synthesis - the final resource count might be different
    Info: Implemented 10 input pins
    Info: Implemented 9 output pins
    Info: Implemented 29 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings
    Info: Processing ended: Sat Dec 29 12:42:03 2007
    Info: Elapsed time: 00:00:02