count.map.qmsg

一个用VHDL写的倒计时程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 29 12:42:01 2007 " "Info: Processing started: Sat Dec 29 12:42:01 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off count -c count " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off count -c count" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "count.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file count.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 count-five " "Info: Found design unit 1: count-five" {  } { { "count.vhd" "" { Text "E:/test2/counnt/count.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 count " "Info: Found entity 1: count" {  } { { "count.vhd" "" { Text "E:/test2/counnt/count.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "count " "Info: Elaborating entity \"count\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sta count.vhd(19) " "Warning (10492): VHDL Process Statement warning at count.vhd(19): signal \"sta\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "count.vhd" "" { Text "E:/test2/counnt/count.vhd" 19 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "ini count.vhd(19) " "Warning (10492): VHDL Process Statement warning at count.vhd(19): signal \"ini\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "count.vhd" "" { Text "E:/test2/counnt/count.vhd" 19 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sta count.vhd(20) " "Warning (10492): VHDL Process Statement warning at count.vhd(20): signal \"sta\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "count.vhd" "" { Text "E:/test2/counnt/count.vhd" 20 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sta count.vhd(24) " "Warning (10492): VHDL Process Statement warning at count.vhd(24): signal \"sta\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "count.vhd" "" { Text "E:/test2/counnt/count.vhd" 24 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "num count.vhd(16) " "Warning (10631): VHDL Process Statement warning at count.vhd(16): inferring latch(es) for signal or variable \"num\", which holds its previous value in one or more paths through the process" {  } { { "count.vhd" "" { Text "E:/test2/counnt/count.vhd" 16 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "sta count.vhd(16) " "Warning (10631): VHDL Process Statement warning at count.vhd(16): inferring latch(es) for signal or variable \"sta\", which holds its previous value in one or more paths through the process" {  } { { "count.vhd" "" { Text "E:/test2/counnt/count.vhd" 16 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "finish count.vhd(16) " "Warning (10631): VHDL Process Statement warning at count.vhd(16): inferring latch(es) for signal or variable \"finish\", which holds its previous value in one or more paths through the process" {  } { { "count.vhd" "" { Text "E:/test2/counnt/count.vhd" 16 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "finish count.vhd(16) " "Info (10041): Verilog HDL or VHDL info at count.vhd(16): inferred latch for \"finish\"" {  } { { "count.vhd" "" { Text "E:/test2/counnt/count.vhd" 16 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "sta\[0\] count.vhd(16) " "Info (10041): Verilog HDL or VHDL info at count.vhd(16): inferred latch for \"sta\[0\]\"" {  } { { "count.vhd" "" { Text "E:/test2/counnt/count.vhd" 16 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "sta\[1\] count.vhd(16) " "Info (10041): Verilog HDL or VHDL info at count.vhd(16): inferred latch for \"sta\[1\]\"" {  } { { "count.vhd" "" { Text "E:/test2/counnt/count.vhd" 16 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "1 " "Warning: Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "t1a " "Warning: No output dependent on input pin \"t1a\"" {  } { { "count.vhd" "" { Text "E:/test2/counnt/count.vhd" 6 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "48 " "Info: Implemented 48 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "10 " "Info: Implemented 10 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "9 " "Info: Implemented 9 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "29 " "Info: Implemented 29 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 9 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 29 12:42:03 2007 " "Info: Processing ended: Sat Dec 29 12:42:03 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}