freq_div1min.vhd

一个用VHDL程序写成的VHDL程序

library ieee;
use ieee.std_logic_1164.all;
entity freq_div1min is
port(fout0:in std_logic;  --clk=64Hz
     fout1: out  std_logic);
end entity freq_div1min;
architecture one of freq_div1min is
  signal count:integer range 0 to 60;--1min freq_div
  signal mid:std_logic;
begin
process(fout0)
begin
if fout0'event and fout0='1' then
  if count=29 then
  count<=0;
  mid<=not mid;
else count<=count+1;
end if;
fout1<=mid;
end if;
end process;
end architecture one;