state.vhd

一个用VHDL程序写成的VHDL程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity state is
port(clk : in std_logic;
     t10_ena :out std_logic;
     t20_ena:out std_logic;
     t10a   :in std_logic;
     t20a   :in std_logic;
     finishb:in std_logic;
     start:  in std_logic;
     reset:   in std_logic;
     led:    out std_logic_vector(2 downto 0);
     motor :  out  std_logic_vector(1 downto 0)
     );
end entity;
architecture one of state is
type states is (st0,st1,st2,st3,st4);
signal c_st:states;
begin
com:process(clk,reset,t20a,t10a)
begin
if reset='1' or finishb='1' or start='0' then 
     c_st<=st0; motor<="00";led<="000";t10_ena<='0';t20_ena<='0';
elsif  clk'event and clk='1' then
case c_st is
when st0 => c_st<=st1;t20_ena<='1';t10_ena<='0';
when st1=>  led<="001";motor<="01";
            if t20a='1' then c_st<=st2;t20_ena<='0';t10_ena<='1';
            else c_st<=st1;t20_ena<='1';t10_ena<='0';
           end if;
when st2=>  led<="010";motor<="00";
            if t10a='1' then c_st<=st3;t20_ena<='1';t10_ena<='0';
           else c_st<=st2;t20_ena<='0';t10_ena<='1';
           end if;
when st3=>  led<="100";motor<="10";
            if t20a='1' then c_st<=st4;t20_ena<='0';t10_ena<='1';
           else c_st<=st3;t20_ena<='1';t10_ena<='0';
           end if;
when st4=>  led<="010";motor<="00";
            if t10a='1' then c_st<=st1;t20_ena<='1';t10_ena<='0';
           else c_st<=st4;t20_ena<='0';t10_ena<='1';
           end if;
when others =>c_st<=st0;
end case;
end if;
end process;
end one;