wash.map.qmsg

一个用VHDL程序写成的VHDL程序

{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "ini count.vhd(21) " "Warning (10492): VHDL Process Statement warning at count.vhd(21): signal \"ini\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "count.vhd" "" { Text "E:/wash/count.vhd" 21 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "freq_div1min freq_div1min:inst8 " "Info: Elaborating entity \"freq_div1min\" for hierarchy \"freq_div1min:inst8\"" {  } { { "wash.bdf" "inst8" { Schematic "E:/wash/wash.bdf" { { 360 128 224 456 "inst8" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "one one:inst9 " "Info: Elaborating entity \"one\" for hierarchy \"one:inst9\"" {  } { { "wash.bdf" "inst9" { Schematic "E:/wash/wash.bdf" { { 360 -8 88 456 "inst9" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "state state:inst5 " "Info: Elaborating entity \"state\" for hierarchy \"state:inst5\"" {  } { { "wash.bdf" "inst5" { Schematic "E:/wash/wash.bdf" { { 136 232 376 296 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "finishb state.vhd(24) " "Warning (10492): VHDL Process Statement warning at state.vhd(24): signal \"finishb\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "state.vhd" "" { Text "E:/wash/state.vhd" 24 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "start state.vhd(24) " "Warning (10492): VHDL Process Statement warning at state.vhd(24): signal \"start\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "state.vhd" "" { Text "E:/wash/state.vhd" 24 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ten ten:inst2 " "Info: Elaborating entity \"ten\" for hierarchy \"ten:inst2\"" {  } { { "wash.bdf" "inst2" { Schematic "E:/wash/wash.bdf" { { 8 424 520 104 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "twenty twenty:inst3 " "Info: Elaborating entity \"twenty\" for hierarchy \"twenty:inst3\"" {  } { { "wash.bdf" "inst3" { Schematic "E:/wash/wash.bdf" { { 112 456 552 208 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "state:inst5\|motor\[0\] state:inst5\|led\[0\] " "Info: Duplicate register \"state:inst5\|motor\[0\]\" merged to single register \"state:inst5\|led\[0\]\"" {  } { { "state.vhd" "" { Text "E:/wash/state.vhd" 24 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "state:inst5\|motor\[1\] state:inst5\|led\[2\] " "Info: Duplicate register \"state:inst5\|motor\[1\]\" merged to single register \"state:inst5\|led\[2\]\"" {  } { { "state.vhd" "" { Text "E:/wash/state.vhd" 24 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|wash\|state:inst5\|c_st 5 " "Info: State machine \"\|wash\|state:inst5\|c_st\" contains 5 states" {  } { { "state.vhd" "" { Text "E:/wash/state.vhd" 20 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|wash\|state:inst5\|c_st " "Info: Selected Auto state machine encoding method for state machine \"\|wash\|state:inst5\|c_st\"" {  } { { "state.vhd" "" { Text "E:/wash/state.vhd" 20 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|wash\|state:inst5\|c_st " "Info: Encoding result for state machine \"\|wash\|state:inst5\|c_st\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "5 " "Info: Completed encoding using 5 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state:inst5\|c_st.st4 " "Info: Encoded state bit \"state:inst5\|c_st.st4\"" {  } { { "state.vhd" "" { Text "E:/wash/state.vhd" 24 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state:inst5\|c_st.st3 " "Info: Encoded state bit \"state:inst5\|c_st.st3\"" {  } { { "state.vhd" "" { Text "E:/wash/state.vhd" 24 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state:inst5\|c_st.st2 " "Info: Encoded state bit \"state:inst5\|c_st.st2\"" {  } { { "state.vhd" "" { Text "E:/wash/state.vhd" 24 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state:inst5\|c_st.st1 " "Info: Encoded state bit \"state:inst5\|c_st.st1\"" {  } { { "state.vhd" "" { Text "E:/wash/state.vhd" 24 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state:inst5\|c_st.st0 " "Info: Encoded state bit \"state:inst5\|c_st.st0\"" {  } { { "state.vhd" "" { Text "E:/wash/state.vhd" 24 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|wash\|state:inst5\|c_st.st0 00000 " "Info: State \"\|wash\|state:inst5\|c_st.st0\" uses code string \"00000\"" {  } { { "state.vhd" "" { Text "E:/wash/state.vhd" 24 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|wash\|state:inst5\|c_st.st1 00011 " "Info: State \"\|wash\|state:inst5\|c_st.st1\" uses code string \"00011\"" {  } { { "state.vhd" "" { Text "E:/wash/state.vhd" 24 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|wash\|state:inst5\|c_st.st2 00101 " "Info: State \"\|wash\|state:inst5\|c_st.st2\" uses code string \"00101\"" {  } { { "state.vhd" "" { Text "E:/wash/state.vhd" 24 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|wash\|state:inst5\|c_st.st3 01001 " "Info: State \"\|wash\|state:inst5\|c_st.st3\" uses code string \"01001\"" {  } { { "state.vhd" "" { Text "E:/wash/state.vhd" 24 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|wash\|state:inst5\|c_st.st4 10001 " "Info: State \"\|wash\|state:inst5\|c_st.st4\" uses code string \"10001\"" {  } { { "state.vhd" "" { Text "E:/wash/state.vhd" 24 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "state.vhd" "" { Text "E:/wash/state.vhd" 20 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "144 " "Info: Implemented 144 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "12 " "Info: Implemented 12 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "14 " "Info: Implemented 14 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "118 " "Info: Implemented 118 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 31 23:29:08 2007 " "Info: Processing ended: Mon Dec 31 23:29:08 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}