wash.tan.qmsg

一个用VHDL程序写成的VHDL程序

{ "Info" "ITDB_FULL_TPD_RESULT" "clk warm 7.730 ns Longest " "Info: Longest tpd from source pin \"clk\" to destination pin \"warm\" is 7.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 51 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 51; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "wash.bdf" "" { Schematic "E:/wash/wash.bdf" { { 48 -16 152 64 "clk" "" } { 152 192 232 168 "clk" "" } { 40 152 184 56 "clk" "" } { 128 416 456 144 "clk" "" } { 24 376 424 40 "clk" "" } { 328 536 568 344 "clk" "" } { 376 -48 -8 392 "clk" "" } { 360 296 336 376 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.316 ns) + CELL(0.292 ns) 3.077 ns warming:inst4\|warn~9 2 COMB LC_X6_Y13_N8 1 " "Info: 2: + IC(1.316 ns) + CELL(0.292 ns) = 3.077 ns; Loc. = LC_X6_Y13_N8; Fanout = 1; COMB Node = 'warming:inst4\|warn~9'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.608 ns" { clk warming:inst4|warn~9 } "NODE_NAME" } } { "warming.vhd" "" { Text "E:/wash/warming.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.545 ns) + CELL(2.108 ns) 7.730 ns warm 3 PIN PIN_68 0 " "Info: 3: + IC(2.545 ns) + CELL(2.108 ns) = 7.730 ns; Loc. = PIN_68; Fanout = 0; PIN Node = 'warm'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.653 ns" { warming:inst4|warn~9 warm } "NODE_NAME" } } { "wash.bdf" "" { Schematic "E:/wash/wash.bdf" { { 336 712 888 352 "warm" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.869 ns ( 50.05 % ) " "Info: Total cell delay = 3.869 ns ( 50.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.861 ns ( 49.95 % ) " "Info: Total interconnect delay = 3.861 ns ( 49.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.730 ns" { clk warming:inst4|warn~9 warm } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.730 ns" { clk clk~out0 warming:inst4|warn~9 warm } { 0.000ns 0.000ns 1.316ns 2.545ns } { 0.000ns 1.469ns 0.292ns 2.108ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "count:inst\|num\[2\] start clk 0.995 ns register " "Info: th for register \"count:inst\|num\[2\]\" (data pin = \"start\", clock pin = \"clk\") is 0.995 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 11.858 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 11.858 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 51 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 51; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "wash.bdf" "" { Schematic "E:/wash/wash.bdf" { { 48 -16 152 64 "clk" "" } { 152 192 232 168 "clk" "" } { 40 152 184 56 "clk" "" } { 128 416 456 144 "clk" "" } { 24 376 424 40 "clk" "" } { 328 536 568 344 "clk" "" } { 376 -48 -8 392 "clk" "" } { 360 296 336 376 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.935 ns) 3.166 ns one:inst9\|fout 2 REG LC_X27_Y10_N4 8 " "Info: 2: + IC(0.762 ns) + CELL(0.935 ns) = 3.166 ns; Loc. = LC_X27_Y10_N4; Fanout = 8; REG Node = 'one:inst9\|fout'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.697 ns" { clk one:inst9|fout } "NODE_NAME" } } { "one.vhd" "" { Text "E:/wash/one.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.506 ns) + CELL(0.935 ns) 7.607 ns freq_div1min:inst8\|fout1 3 REG LC_X8_Y10_N4 8 " "Info: 3: + IC(3.506 ns) + CELL(0.935 ns) = 7.607 ns; Loc. = LC_X8_Y10_N4; Fanout = 8; REG Node = 'freq_div1min:inst8\|fout1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.441 ns" { one:inst9|fout freq_div1min:inst8|fout1 } "NODE_NAME" } } { "freq_div1min.vhd" "" { Text "E:/wash/freq_div1min.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.540 ns) + CELL(0.711 ns) 11.858 ns count:inst\|num\[2\] 4 REG LC_X5_Y13_N2 6 " "Info: 4: + IC(3.540 ns) + CELL(0.711 ns) = 11.858 ns; Loc. = LC_X5_Y13_N2; Fanout = 6; REG Node = 'count:inst\|num\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.251 ns" { freq_div1min:inst8|fout1 count:inst|num[2] } "NODE_NAME" } } { "count.vhd" "" { Text "E:/wash/count.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns ( 34.15 % ) " "Info: Total cell delay = 4.050 ns ( 34.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.808 ns ( 65.85 % ) " "Info: Total interconnect delay = 7.808 ns ( 65.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.858 ns" { clk one:inst9|fout freq_div1min:inst8|fout1 count:inst|num[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.858 ns" { clk clk~out0 one:inst9|fout freq_div1min:inst8|fout1 count:inst|num[2] } { 0.000ns 0.000ns 0.762ns 3.506ns 3.540ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "count.vhd" "" { Text "E:/wash/count.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.878 ns - Shortest pin register " "Info: - Shortest pin to register delay is 10.878 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns start 1 PIN PIN_83 10 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_83; Fanout = 10; PIN Node = 'start'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { start } "NODE_NAME" } } { "wash.bdf" "" { Schematic "E:/wash/wash.bdf" { { 112 -16 152 128 "start" "" } { 216 200 232 232 "start" "" } { 104 152 182 120 "start" "" } { 392 304 336 408 "start" "" } { 392 -64 -8 408 "start" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.306 ns) + CELL(0.114 ns) 8.895 ns count:inst\|process0~0 2 COMB LC_X6_Y13_N7 8 " "Info: 2: + IC(7.306 ns) + CELL(0.114 ns) = 8.895 ns; Loc. = LC_X6_Y13_N7; Fanout = 8; COMB Node = 'count:inst\|process0~0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.420 ns" { start count:inst|process0~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.116 ns) + CELL(0.867 ns) 10.878 ns count:inst\|num\[2\] 3 REG LC_X5_Y13_N2 6 " "Info: 3: + IC(1.116 ns) + CELL(0.867 ns) = 10.878 ns; Loc. = LC_X5_Y13_N2; Fanout = 6; REG Node = 'count:inst\|num\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.983 ns" { count:inst|process0~0 count:inst|num[2] } "NODE_NAME" } } { "count.vhd" "" { Text "E:/wash/count.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.456 ns ( 22.58 % ) " "Info: Total cell delay = 2.456 ns ( 22.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.422 ns ( 77.42 % ) " "Info: Total interconnect delay = 8.422 ns ( 77.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.878 ns" { start count:inst|process0~0 count:inst|num[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "10.878 ns" { start start~out0 count:inst|process0~0 count:inst|num[2] } { 0.000ns 0.000ns 7.306ns 1.116ns } { 0.000ns 1.475ns 0.114ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.858 ns" { clk one:inst9|fout freq_div1min:inst8|fout1 count:inst|num[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.858 ns" { clk clk~out0 one:inst9|fout freq_div1min:inst8|fout1 count:inst|num[2] } { 0.000ns 0.000ns 0.762ns 3.506ns 3.540ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.878 ns" { start count:inst|process0~0 count:inst|num[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "10.878 ns" { start start~out0 count:inst|process0~0 count:inst|num[2] } { 0.000ns 0.000ns 7.306ns 1.116ns } { 0.000ns 1.475ns 0.114ns 0.867ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 31 23:29:19 2007 " "Info: Processing ended: Mon Dec 31 23:29:19 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}