wash.tan.qmsg

一个用VHDL程序写成的VHDL程序

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "one:inst9\|fout " "Info: Detected ripple clock \"one:inst9\|fout\" as buffer" {  } { { "one.vhd" "" { Text "E:/wash/one.vhd" 6 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "one:inst9\|fout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "freq_div1min:inst8\|fout1 " "Info: Detected ripple clock \"freq_div1min:inst8\|fout1\" as buffer" {  } { { "freq_div1min.vhd" "" { Text "E:/wash/freq_div1min.vhd" 5 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "freq_div1min:inst8\|fout1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register count:inst\|num\[0\] register count:inst\|finish 89.81 MHz 11.135 ns Internal " "Info: Clock \"clk\" has Internal fmax of 89.81 MHz between source register \"count:inst\|num\[0\]\" and destination register \"count:inst\|finish\" (period= 11.135 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.974 ns + Longest register register " "Info: + Longest register to register delay is 1.974 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count:inst\|num\[0\] 1 REG LC_X5_Y13_N0 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y13_N0; Fanout = 5; REG Node = 'count:inst\|num\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { count:inst|num[0] } "NODE_NAME" } } { "count.vhd" "" { Text "E:/wash/count.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.767 ns) + CELL(0.292 ns) 1.059 ns count:inst\|Equal1~66 2 COMB LC_X6_Y13_N9 2 " "Info: 2: + IC(0.767 ns) + CELL(0.292 ns) = 1.059 ns; Loc. = LC_X6_Y13_N9; Fanout = 2; COMB Node = 'count:inst\|Equal1~66'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.059 ns" { count:inst|num[0] count:inst|Equal1~66 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.437 ns) + CELL(0.478 ns) 1.974 ns count:inst\|finish 3 REG LC_X6_Y13_N3 2 " "Info: 3: + IC(0.437 ns) + CELL(0.478 ns) = 1.974 ns; Loc. = LC_X6_Y13_N3; Fanout = 2; REG Node = 'count:inst\|finish'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.915 ns" { count:inst|Equal1~66 count:inst|finish } "NODE_NAME" } } { "count.vhd" "" { Text "E:/wash/count.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.770 ns ( 39.01 % ) " "Info: Total cell delay = 0.770 ns ( 39.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.204 ns ( 60.99 % ) " "Info: Total interconnect delay = 1.204 ns ( 60.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.974 ns" { count:inst|num[0] count:inst|Equal1~66 count:inst|finish } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.974 ns" { count:inst|num[0] count:inst|Equal1~66 count:inst|finish } { 0.000ns 0.767ns 0.437ns } { 0.000ns 0.292ns 0.478ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-8.900 ns - Smallest " "Info: - Smallest clock skew is -8.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.958 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.958 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 51 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 51; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "wash.bdf" "" { Schematic "E:/wash/wash.bdf" { { 48 -16 152 64 "clk" "" } { 152 192 232 168 "clk" "" } { 40 152 184 56 "clk" "" } { 128 416 456 144 "clk" "" } { 24 376 424 40 "clk" "" } { 328 536 568 344 "clk" "" } { 376 -48 -8 392 "clk" "" } { 360 296 336 376 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.778 ns) + CELL(0.711 ns) 2.958 ns count:inst\|finish 2 REG LC_X6_Y13_N3 2 " "Info: 2: + IC(0.778 ns) + CELL(0.711 ns) = 2.958 ns; Loc. = LC_X6_Y13_N3; Fanout = 2; REG Node = 'count:inst\|finish'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.489 ns" { clk count:inst|finish } "NODE_NAME" } } { "count.vhd" "" { Text "E:/wash/count.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.70 % ) " "Info: Total cell delay = 2.180 ns ( 73.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.778 ns ( 26.30 % ) " "Info: Total interconnect delay = 0.778 ns ( 26.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.958 ns" { clk count:inst|finish } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.958 ns" { clk clk~out0 count:inst|finish } { 0.000ns 0.000ns 0.778ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 11.858 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 11.858 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 51 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 51; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "wash.bdf" "" { Schematic "E:/wash/wash.bdf" { { 48 -16 152 64 "clk" "" } { 152 192 232 168 "clk" "" } { 40 152 184 56 "clk" "" } { 128 416 456 144 "clk" "" } { 24 376 424 40 "clk" "" } { 328 536 568 344 "clk" "" } { 376 -48 -8 392 "clk" "" } { 360 296 336 376 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.935 ns) 3.166 ns one:inst9\|fout 2 REG LC_X27_Y10_N4 8 " "Info: 2: + IC(0.762 ns) + CELL(0.935 ns) = 3.166 ns; Loc. = LC_X27_Y10_N4; Fanout = 8; REG Node = 'one:inst9\|fout'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.697 ns" { clk one:inst9|fout } "NODE_NAME" } } { "one.vhd" "" { Text "E:/wash/one.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.506 ns) + CELL(0.935 ns) 7.607 ns freq_div1min:inst8\|fout1 3 REG LC_X8_Y10_N4 8 " "Info: 3: + IC(3.506 ns) + CELL(0.935 ns) = 7.607 ns; Loc. = LC_X8_Y10_N4; Fanout = 8; REG Node = 'freq_div1min:inst8\|fout1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.441 ns" { one:inst9|fout freq_div1min:inst8|fout1 } "NODE_NAME" } } { "freq_div1min.vhd" "" { Text "E:/wash/freq_div1min.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.540 ns) + CELL(0.711 ns) 11.858 ns count:inst\|num\[0\] 4 REG LC_X5_Y13_N0 5 " "Info: 4: + IC(3.540 ns) + CELL(0.711 ns) = 11.858 ns; Loc. = LC_X5_Y13_N0; Fanout = 5; REG Node = 'count:inst\|num\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.251 ns" { freq_div1min:inst8|fout1 count:inst|num[0] } "NODE_NAME" } } { "count.vhd" "" { Text "E:/wash/count.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns ( 34.15 % ) " "Info: Total cell delay = 4.050 ns ( 34.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.808 ns ( 65.85 % ) " "Info: Total interconnect delay = 7.808 ns ( 65.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.858 ns" { clk one:inst9|fout freq_div1min:inst8|fout1 count:inst|num[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.858 ns" { clk clk~out0 one:inst9|fout freq_div1min:inst8|fout1 count:inst|num[0] } { 0.000ns 0.000ns 0.762ns 3.506ns 3.540ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.958 ns" { clk count:inst|finish } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.958 ns" { clk clk~out0 count:inst|finish } { 0.000ns 0.000ns 0.778ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.858 ns" { clk one:inst9|fout freq_div1min:inst8|fout1 count:inst|num[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.858 ns" { clk clk~out0 one:inst9|fout freq_div1min:inst8|fout1 count:inst|num[0] } { 0.000ns 0.000ns 0.762ns 3.506ns 3.540ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "count.vhd" "" { Text "E:/wash/count.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "count.vhd" "" { Text "E:/wash/count.vhd" 8 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.974 ns" { count:inst|num[0] count:inst|Equal1~66 count:inst|finish } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.974 ns" { count:inst|num[0] count:inst|Equal1~66 count:inst|finish } { 0.000ns 0.767ns 0.437ns } { 0.000ns 0.292ns 0.478ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.958 ns" { clk count:inst|finish } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.958 ns" { clk clk~out0 count:inst|finish } { 0.000ns 0.000ns 0.778ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.858 ns" { clk one:inst9|fout freq_div1min:inst8|fout1 count:inst|num[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.858 ns" { clk clk~out0 one:inst9|fout freq_div1min:inst8|fout1 count:inst|num[0] } { 0.000ns 0.000ns 0.762ns 3.506ns 3.540ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "one:inst9\|fout start clk 6.992 ns register " "Info: tsu for register \"one:inst9\|fout\" (data pin = \"start\", clock pin = \"clk\") is 6.992 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.897 ns + Longest pin register " "Info: + Longest pin to register delay is 9.897 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns start 1 PIN PIN_83 10 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_83; Fanout = 10; PIN Node = 'start'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { start } "NODE_NAME" } } { "wash.bdf" "" { Schematic "E:/wash/wash.bdf" { { 112 -16 152 128 "start" "" } { 216 200 232 232 "start" "" } { 104 152 182 120 "start" "" } { 392 304 336 408 "start" "" } { 392 -64 -8 408 "start" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.555 ns) + CELL(0.867 ns) 9.897 ns one:inst9\|fout 2 REG LC_X27_Y10_N4 8 " "Info: 2: + IC(7.555 ns) + CELL(0.867 ns) = 9.897 ns; Loc. = LC_X27_Y10_N4; Fanout = 8; REG Node = 'one:inst9\|fout'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.422 ns" { start one:inst9|fout } "NODE_NAME" } } { "one.vhd" "" { Text "E:/wash/one.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.342 ns ( 23.66 % ) " "Info: Total cell delay = 2.342 ns ( 23.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.555 ns ( 76.34 % ) " "Info: Total interconnect delay = 7.555 ns ( 76.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.897 ns" { start one:inst9|fout } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "9.897 ns" { start start~out0 one:inst9|fout } { 0.000ns 0.000ns 7.555ns } { 0.000ns 1.475ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "one.vhd" "" { Text "E:/wash/one.vhd" 6 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.942 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 51 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 51; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "wash.bdf" "" { Schematic "E:/wash/wash.bdf" { { 48 -16 152 64 "clk" "" } { 152 192 232 168 "clk" "" } { 40 152 184 56 "clk" "" } { 128 416 456 144 "clk" "" } { 24 376 424 40 "clk" "" } { 328 536 568 344 "clk" "" } { 376 -48 -8 392 "clk" "" } { 360 296 336 376 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.711 ns) 2.942 ns one:inst9\|fout 2 REG LC_X27_Y10_N4 8 " "Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X27_Y10_N4; Fanout = 8; REG Node = 'one:inst9\|fout'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.473 ns" { clk one:inst9|fout } "NODE_NAME" } } { "one.vhd" "" { Text "E:/wash/one.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.10 % ) " "Info: Total cell delay = 2.180 ns ( 74.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns ( 25.90 % ) " "Info: Total interconnect delay = 0.762 ns ( 25.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.942 ns" { clk one:inst9|fout } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.942 ns" { clk clk~out0 one:inst9|fout } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.897 ns" { start one:inst9|fout } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "9.897 ns" { start start~out0 one:inst9|fout } { 0.000ns 0.000ns 7.555ns } { 0.000ns 1.475ns 0.867ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.942 ns" { clk one:inst9|fout } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.942 ns" { clk clk~out0 one:inst9|fout } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk warm count:inst\|finish 8.479 ns register " "Info: tco from clock \"clk\" to destination pin \"warm\" through register \"count:inst\|finish\" is 8.479 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.958 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.958 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 51 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 51; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "wash.bdf" "" { Schematic "E:/wash/wash.bdf" { { 48 -16 152 64 "clk" "" } { 152 192 232 168 "clk" "" } { 40 152 184 56 "clk" "" } { 128 416 456 144 "clk" "" } { 24 376 424 40 "clk" "" } { 328 536 568 344 "clk" "" } { 376 -48 -8 392 "clk" "" } { 360 296 336 376 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.778 ns) + CELL(0.711 ns) 2.958 ns count:inst\|finish 2 REG LC_X6_Y13_N3 2 " "Info: 2: + IC(0.778 ns) + CELL(0.711 ns) = 2.958 ns; Loc. = LC_X6_Y13_N3; Fanout = 2; REG Node = 'count:inst\|finish'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.489 ns" { clk count:inst|finish } "NODE_NAME" } } { "count.vhd" "" { Text "E:/wash/count.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.70 % ) " "Info: Total cell delay = 2.180 ns ( 73.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.778 ns ( 26.30 % ) " "Info: Total interconnect delay = 0.778 ns ( 26.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.958 ns" { clk count:inst|finish } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.958 ns" { clk clk~out0 count:inst|finish } { 0.000ns 0.000ns 0.778ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "count.vhd" "" { Text "E:/wash/count.vhd" 8 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.297 ns + Longest register pin " "Info: + Longest register to pin delay is 5.297 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count:inst\|finish 1 REG LC_X6_Y13_N3 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y13_N3; Fanout = 2; REG Node = 'count:inst\|finish'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { count:inst|finish } "NODE_NAME" } } { "count.vhd" "" { Text "E:/wash/count.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.530 ns) + CELL(0.114 ns) 0.644 ns warming:inst4\|warn~9 2 COMB LC_X6_Y13_N8 1 " "Info: 2: + IC(0.530 ns) + CELL(0.114 ns) = 0.644 ns; Loc. = LC_X6_Y13_N8; Fanout = 1; COMB Node = 'warming:inst4\|warn~9'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.644 ns" { count:inst|finish warming:inst4|warn~9 } "NODE_NAME" } } { "warming.vhd" "" { Text "E:/wash/warming.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.545 ns) + CELL(2.108 ns) 5.297 ns warm 3 PIN PIN_68 0 " "Info: 3: + IC(2.545 ns) + CELL(2.108 ns) = 5.297 ns; Loc. = PIN_68; Fanout = 0; PIN Node = 'warm'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.653 ns" { warming:inst4|warn~9 warm } "NODE_NAME" } } { "wash.bdf" "" { Schematic "E:/wash/wash.bdf" { { 336 712 888 352 "warm" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.222 ns ( 41.95 % ) " "Info: Total cell delay = 2.222 ns ( 41.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.075 ns ( 58.05 % ) " "Info: Total interconnect delay = 3.075 ns ( 58.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.297 ns" { count:inst|finish warming:inst4|warn~9 warm } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.297 ns" { count:inst|finish warming:inst4|warn~9 warm } { 0.000ns 0.530ns 2.545ns } { 0.000ns 0.114ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.958 ns" { clk count:inst|finish } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.958 ns" { clk clk~out0 count:inst|finish } { 0.000ns 0.000ns 0.778ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.297 ns" { count:inst|finish warming:inst4|warn~9 warm } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.297 ns" { count:inst|finish warming:inst4|warn~9 warm } { 0.000ns 0.530ns 2.545ns } { 0.000ns 0.114ns 2.108ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}