wash.map.rpt

一个用VHDL程序写成的VHDL程序

+----------+----------+----------+----------+----------+----------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 66    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 20    ;
; Number of registers using Asynchronous Load  ; 19    ;
; Number of registers using Clock Enable       ; 15    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; state:inst5|c_st.st0                   ; 6       ;
; Total number of inverted registers = 1 ;         ;
+----------------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |wash|state:inst5|t20_ena  ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+----------------------------------------+
; Source assignments for count:inst      ;
+----------------+-------+------+--------+
; Assignment     ; Value ; From ; To     ;
+----------------+-------+------+--------+
; POWER_UP_LEVEL ; High  ; -    ; num[0] ;
; POWER_UP_LEVEL ; High  ; -    ; num[1] ;
; POWER_UP_LEVEL ; High  ; -    ; num[2] ;
; POWER_UP_LEVEL ; High  ; -    ; num[3] ;
; POWER_UP_LEVEL ; High  ; -    ; num[4] ;
; POWER_UP_LEVEL ; High  ; -    ; num[5] ;
; POWER_UP_LEVEL ; High  ; -    ; num[6] ;
; POWER_UP_LEVEL ; High  ; -    ; num[7] ;
+----------------+-------+------+--------+


+-------------------------------------------+
; Source assignments for freq_div1min:inst8 ;
+----------------+-------+------+-----------+
; Assignment     ; Value ; From ; To        ;
+----------------+-------+------+-----------+
; POWER_UP_LEVEL ; Low   ; -    ; count[0]  ;
; POWER_UP_LEVEL ; Low   ; -    ; count[1]  ;
; POWER_UP_LEVEL ; Low   ; -    ; count[2]  ;
; POWER_UP_LEVEL ; Low   ; -    ; count[3]  ;
; POWER_UP_LEVEL ; Low   ; -    ; count[4]  ;
; POWER_UP_LEVEL ; Low   ; -    ; count[5]  ;
+----------------+-------+------+-----------+


+------------------------------------------+
; Source assignments for one:inst9         ;
+----------------+-------+------+----------+
; Assignment     ; Value ; From ; To       ;
+----------------+-------+------+----------+
; POWER_UP_LEVEL ; Low   ; -    ; count[0] ;
; POWER_UP_LEVEL ; Low   ; -    ; count[1] ;
; POWER_UP_LEVEL ; Low   ; -    ; count[2] ;
; POWER_UP_LEVEL ; Low   ; -    ; count[3] ;
; POWER_UP_LEVEL ; Low   ; -    ; count[4] ;
; POWER_UP_LEVEL ; Low   ; -    ; count[5] ;
+----------------+-------+------+----------+


+------------------------------------------+
; Source assignments for state:inst5       ;
+----------------+-------+------+----------+
; Assignment     ; Value ; From ; To       ;
+----------------+-------+------+----------+
; POWER_UP_LEVEL ; Low   ; -    ; c_st.st4 ;
; POWER_UP_LEVEL ; Low   ; -    ; c_st.st3 ;
; POWER_UP_LEVEL ; Low   ; -    ; c_st.st2 ;
; POWER_UP_LEVEL ; Low   ; -    ; c_st.st1 ;
; POWER_UP_LEVEL ; High  ; -    ; c_st.st0 ;
+----------------+-------+------+----------+


+----------------------------------------+
; Source assignments for ten:inst2       ;
+----------------+-------+------+--------+
; Assignment     ; Value ; From ; To     ;
+----------------+-------+------+--------+
; POWER_UP_LEVEL ; Low   ; -    ; num[1] ;
; POWER_UP_LEVEL ; Low   ; -    ; num[0] ;
; POWER_UP_LEVEL ; Low   ; -    ; num[2] ;
; POWER_UP_LEVEL ; Low   ; -    ; num[3] ;
; POWER_UP_LEVEL ; Low   ; -    ; num[4] ;
; POWER_UP_LEVEL ; Low   ; -    ; num[5] ;
; POWER_UP_LEVEL ; Low   ; -    ; num[6] ;
; POWER_UP_LEVEL ; Low   ; -    ; num[7] ;
; POWER_UP_LEVEL ; Low   ; -    ; num[8] ;
; POWER_UP_LEVEL ; Low   ; -    ; num[9] ;
+----------------+-------+------+--------+


+-----------------------------------------+
; Source assignments for twenty:inst3     ;
+----------------+-------+------+---------+
; Assignment     ; Value ; From ; To      ;
+----------------+-------+------+---------+
; POWER_UP_LEVEL ; Low   ; -    ; num[1]  ;
; POWER_UP_LEVEL ; Low   ; -    ; num[0]  ;
; POWER_UP_LEVEL ; Low   ; -    ; num[2]  ;
; POWER_UP_LEVEL ; Low   ; -    ; num[3]  ;
; POWER_UP_LEVEL ; Low   ; -    ; num[4]  ;
; POWER_UP_LEVEL ; Low   ; -    ; num[5]  ;
; POWER_UP_LEVEL ; Low   ; -    ; num[6]  ;
; POWER_UP_LEVEL ; Low   ; -    ; num[7]  ;
; POWER_UP_LEVEL ; Low   ; -    ; num[8]  ;
; POWER_UP_LEVEL ; Low   ; -    ; num[9]  ;
; POWER_UP_LEVEL ; Low   ; -    ; num[10] ;
+----------------+-------+------+---------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Mon Dec 31 23:29:06 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off wash -c wash
Info: Found 2 design units, including 1 entities, in source file count.vhd
    Info: Found design unit 1: count-five
    Info: Found entity 1: count
Info: Found 2 design units, including 1 entities, in source file one.vhd
    Info: Found design unit 1: one-one
    Info: Found entity 1: one
Info: Found 2 design units, including 1 entities, in source file state.vhd
    Info: Found design unit 1: state-one
    Info: Found entity 1: state
Info: Found 2 design units, including 1 entities, in source file ten.vhd
    Info: Found design unit 1: ten-three
    Info: Found entity 1: ten
Info: Found 2 design units, including 1 entities, in source file twenty.vhd
    Info: Found design unit 1: twenty-four
    Info: Found entity 1: twenty
Info: Found 2 design units, including 1 entities, in source file warming.vhd
    Info: Found design unit 1: warming-six
    Info: Found entity 1: warming
Info: Found 1 design units, including 1 entities, in source file wash.bdf
    Info: Found entity 1: wash
Info: Found 2 design units, including 1 entities, in source file freq_div1min.vhd
    Info: Found design unit 1: freq_div1min-one
    Info: Found entity 1: freq_div1min
Info: Elaborating entity "wash" for the top level hierarchy
Info: Elaborating entity "warming" for hierarchy "warming:inst4"
Warning (10492): VHDL Process Statement warning at warming.vhd(14): signal "finishc" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "count" for hierarchy "count:inst"
Warning (10492): VHDL Process Statement warning at count.vhd(21): signal "enter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at count.vhd(21): signal "ini" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "freq_div1min" for hierarchy "freq_div1min:inst8"
Info: Elaborating entity "one" for hierarchy "one:inst9"
Info: Elaborating entity "state" for hierarchy "state:inst5"
Warning (10492): VHDL Process Statement warning at state.vhd(24): signal "finishb" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at state.vhd(24): signal "start" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "ten" for hierarchy "ten:inst2"
Info: Elaborating entity "twenty" for hierarchy "twenty:inst3"
Info: Duplicate registers merged to single register
    Info: Duplicate register "state:inst5|motor[0]" merged to single register "state:inst5|led[0]"
    Info: Duplicate register "state:inst5|motor[1]" merged to single register "state:inst5|led[2]"
Info: State machine "|wash|state:inst5|c_st" contains 5 states
Info: Selected Auto state machine encoding method for state machine "|wash|state:inst5|c_st"
Info: Encoding result for state machine "|wash|state:inst5|c_st"
    Info: Completed encoding using 5 state bits
        Info: Encoded state bit "state:inst5|c_st.st4"
        Info: Encoded state bit "state:inst5|c_st.st3"
        Info: Encoded state bit "state:inst5|c_st.st2"
        Info: Encoded state bit "state:inst5|c_st.st1"
        Info: Encoded state bit "state:inst5|c_st.st0"
    Info: State "|wash|state:inst5|c_st.st0" uses code string "00000"
    Info: State "|wash|state:inst5|c_st.st1" uses code string "00011"
    Info: State "|wash|state:inst5|c_st.st2" uses code string "00101"
    Info: State "|wash|state:inst5|c_st.st3" uses code string "01001"
    Info: State "|wash|state:inst5|c_st.st4" uses code string "10001"
Info: Implemented 144 device resources after synthesis - the final resource count might be different
    Info: Implemented 12 input pins
    Info: Implemented 14 output pins
    Info: Implemented 118 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings
    Info: Processing ended: Mon Dec 31 23:29:08 2007
    Info: Elapsed time: 00:00:02