one.vhd

一个用VHDL程序写成的VHDL程序

--1S的分频
library ieee;
use ieee.std_logic_1164.all;
entity one is
port(clk:in std_logic;  --clk=64Hz
     fout:out std_logic;
     start: in bit);
end entity one;
architecture one of one is
  signal count:integer range 0 to 32;--1s freq_div
  signal mid:std_logic;
begin
process(clk,start)
begin
if start='1' then
if clk'event and clk='1' then
  if count=31 then
  count<=0;
  mid<=not mid;
else count<=count+1;
end if;
fout<=mid;
end if;
end if;
end process;
end architecture one;