ten.vhd

一个用VHDL程序写成的VHDL程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ten is
port(clk :in std_logic;
     t10_en :in std_logic;
     t10:out std_logic
     );
end entity ten;
architecture three of ten is
signal num : integer range 640 downto 0:=0;
begin
process(clk,t10_en)
begin 
if(t10_en='1') then 
     if clk'event and clk='1' then 
        if num=639 then num<=0;
         else num<=num+1;
end if;
end if;
--end if;
elsif t10_en='0' then num<=0;
end if ;
end process;
process(clk)
begin
if clk'event and clk='1' then
     if(num=639) then t10<='1';
     else t10<='0';
end if;
end if;
end process;
end architecture three;