colorbar.map.qmsg

this a sample about the VGA BLUE,the function of this code is show blue in VGA,it s default installa

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jun 27 23:33:38 2005 " "Info: Processing started: Mon Jun 27 23:33:38 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ColorBar -c ColorBar " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ColorBar -c ColorBar" {  } {  } 0}
{ "Warning" "WVRFX_VERI_IGNORED_ANONYMOUS_PORT" "vga_blue vga_blue.v(63) " "Warning: Verilog Module Declaration warning at vga_blue.v(63): ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module \"vga_blue\"" {  } { { "../src/vga_blue.v" "" { Text "D:/RedLogic/RCII_samples/VGA_BLUE/src/vga_blue.v" 63 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../src/vga_blue.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../src/vga_blue.v" { { "Info" "ISGN_ENTITY_NAME" "1 vga_blue " "Info: Found entity 1: vga_blue" {  } { { "../src/vga_blue.v" "" { Text "D:/RedLogic/RCII_samples/VGA_BLUE/src/vga_blue.v" 58 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../Src/BlueScreen.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../Src/BlueScreen.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 BlueScreen " "Info: Found entity 1: BlueScreen" {  } { { "../Src/BlueScreen.bdf" "" { Schematic "D:/RedLogic/RCII_samples/VGA_BLUE/Src/BlueScreen.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "BlueScreen " "Info: Elaborating entity \"BlueScreen\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WGDFX_UNRESOLVED_PARAMETER" "H_PIXELS 32'b00000000000000000000001100100110 " "Warning: Can't find a definition for parameter H_PIXELS -- assuming 32'b00000000000000000000001100100110 was intended to be a quoted string" {  } { { "../Src/BlueScreen.bdf" "" { Schematic "D:/RedLogic/RCII_samples/VGA_BLUE/Src/BlueScreen.bdf" { { 216 344 480 312 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_UNRESOLVED_PARAMETER" "H_FRONTPORCH 32'b00000000000000000000000000100101 " "Warning: Can't find a definition for parameter H_FRONTPORCH -- assuming 32'b00000000000000000000000000100101 was intended to be a quoted string" {  } { { "../Src/BlueScreen.bdf" "" { Schematic "D:/RedLogic/RCII_samples/VGA_BLUE/Src/BlueScreen.bdf" { { 216 344 480 312 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_UNRESOLVED_PARAMETER" "H_SYNCTIME 32'b00000000000000000000000010000000 " "Warning: Can't find a definition for parameter H_SYNCTIME -- assuming 32'b00000000000000000000000010000000 was intended to be a quoted string" {  } { { "../Src/BlueScreen.bdf" "" { Schematic "D:/RedLogic/RCII_samples/VGA_BLUE/Src/BlueScreen.bdf" { { 216 344 480 312 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_UNRESOLVED_PARAMETER" "H_BACKPORCH 32'b00000000000000000000000001010101 " "Warning: Can't find a definition for parameter H_BACKPORCH -- assuming 32'b00000000000000000000000001010101 was intended to be a quoted string" {  } { { "../Src/BlueScreen.bdf" "" { Schematic "D:/RedLogic/RCII_samples/VGA_BLUE/Src/BlueScreen.bdf" { { 216 344 480 312 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_UNRESOLVED_PARAMETER" "H_SYNCSTART 32'b00000000000000000000001101001011 " "Warning: Can't find a definition for parameter H_SYNCSTART -- assuming 32'b00000000000000000000001101001011 was intended to be a quoted string" {  } { { "../Src/BlueScreen.bdf" "" { Schematic "D:/RedLogic/RCII_samples/VGA_BLUE/Src/BlueScreen.bdf" { { 216 344 480 312 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_UNRESOLVED_PARAMETER" "H_SYNCEND 32'b00000000000000000000001111001011 " "Warning: Can't find a definition for parameter H_SYNCEND -- assuming 32'b00000000000000000000001111001011 was intended to be a quoted string" {  } { { "../Src/BlueScreen.bdf" "" { Schematic "D:/RedLogic/RCII_samples/VGA_BLUE/Src/BlueScreen.bdf" { { 216 344 480 312 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_UNRESOLVED_PARAMETER" "H_PERIOD 32'b00000000000000000000010000100000 " "Warning: Can't find a definition for parameter H_PERIOD -- assuming 32'b00000000000000000000010000100000 was intended to be a quoted string" {  } { { "../Src/BlueScreen.bdf" "" { Schematic "D:/RedLogic/RCII_samples/VGA_BLUE/Src/BlueScreen.bdf" { { 216 344 480 312 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_UNRESOLVED_PARAMETER" "V_LINES 32'b00000000000000000000001001011100 " "Warning: Can't find a definition for parameter V_LINES -- assuming 32'b00000000000000000000001001011100 was intended to be a quoted string" {  } { { "../Src/BlueScreen.bdf" "" { Schematic "D:/RedLogic/RCII_samples/VGA_BLUE/Src/BlueScreen.bdf" { { 216 344 480 312 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_UNRESOLVED_PARAMETER" "V_SYNCTIME 32'b00000000000000000000000000000100 " "Warning: Can't find a definition for parameter V_SYNCTIME -- assuming 32'b00000000000000000000000000000100 was intended to be a quoted string" {  } { { "../Src/BlueScreen.bdf" "" { Schematic "D:/RedLogic/RCII_samples/VGA_BLUE/Src/BlueScreen.bdf" { { 216 344 480 312 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_UNRESOLVED_PARAMETER" "V_BACKPORCH 32'b00000000000000000000000000010101 " "Warning: Can't find a definition for parameter V_BACKPORCH -- assuming 32'b00000000000000000000000000010101 was intended to be a quoted string" {  } { { "../Src/BlueScreen.bdf" "" { Schematic "D:/RedLogic/RCII_samples/VGA_BLUE/Src/BlueScreen.bdf" { { 216 344 480 312 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_UNRESOLVED_PARAMETER" "V_SYNCSTART 32'b00000000000000000000001001011011 " "Warning: Can't find a definition for parameter V_SYNCSTART -- assuming 32'b00000000000000000000001001011011 was intended to be a quoted string" {  } { { "../Src/BlueScreen.bdf" "" { Schematic "D:/RedLogic/RCII_samples/VGA_BLUE/Src/BlueScreen.bdf" { { 216 344 480 312 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_UNRESOLVED_PARAMETER" "V_SYNCEND 32'b00000000000000000000001001011111 " "Warning: Can't find a definition for parameter V_SYNCEND -- assuming 32'b00000000000000000000001001011111 was intended to be a quoted string" {  } { { "../Src/BlueScreen.bdf" "" { Schematic "D:/RedLogic/RCII_samples/VGA_BLUE/Src/BlueScreen.bdf" { { 216 344 480 312 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_UNRESOLVED_PARAMETER" "V_PERIOD 32'b00000000000000000000001001110100 " "Warning: Can't find a definition for parameter V_PERIOD -- assuming 32'b00000000000000000000001001110100 was intended to be a quoted string" {  } { { "../Src/BlueScreen.bdf" "" { Schematic "D:/RedLogic/RCII_samples/VGA_BLUE/Src/BlueScreen.bdf" { { 216 344 480 312 "inst" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "vga_blue vga_blue:inst " "Info: Elaborating entity \"vga_blue\" for hierarchy \"vga_blue:inst\"" {  } { { "../Src/BlueScreen.bdf" "inst" { Schematic "D:/RedLogic/RCII_samples/VGA_BLUE/Src/BlueScreen.bdf" { { 216 344 480 312 "inst" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 vga_blue.v(93) " "Warning: Verilog HDL assignment warning at vga_blue.v(93): truncated value with size 32 to match size of target (11)" {  } { { "../src/vga_blue.v" "" { Text "D:/RedLogic/RCII_samples/VGA_BLUE/src/vga_blue.v" 93 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 vga_blue.v(95) " "Warning: Verilog HDL assignment warning at vga_blue.v(95): truncated value with size 32 to match size of target (11)" {  } { { "../src/vga_blue.v" "" { Text "D:/RedLogic/RCII_samples/VGA_BLUE/src/vga_blue.v" 95 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 vga_blue.v(97) " "Warning: Verilog HDL assignment warning at vga_blue.v(97): truncated value with size 32 to match size of target (11)" {  } { { "../src/vga_blue.v" "" { Text "D:/RedLogic/RCII_samples/VGA_BLUE/src/vga_blue.v" 97 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 vga_blue.v(102) " "Warning: Verilog HDL assignment warning at vga_blue.v(102): truncated value with size 32 to match size of target (1)" {  } { { "../src/vga_blue.v" "" { Text "D:/RedLogic/RCII_samples/VGA_BLUE/src/vga_blue.v" 102 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 vga_blue.v(104) " "Warning: Verilog HDL assignment warning at vga_blue.v(104): truncated value with size 32 to match size of target (1)" {  } { { "../src/vga_blue.v" "" { Text "D:/RedLogic/RCII_samples/VGA_BLUE/src/vga_blue.v" 104 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 vga_blue.v(106) " "Warning: Verilog HDL assignment warning at vga_blue.v(106): truncated value with size 32 to match size of target (1)" {  } { { "../src/vga_blue.v" "" { Text "D:/RedLogic/RCII_samples/VGA_BLUE/src/vga_blue.v" 106 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 vga_blue.v(114) " "Warning: Verilog HDL assignment warning at vga_blue.v(114): truncated value with size 32 to match size of target (11)" {  } { { "../src/vga_blue.v" "" { Text "D:/RedLogic/RCII_samples/VGA_BLUE/src/vga_blue.v" 114 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 vga_blue.v(116) " "Warning: Verilog HDL assignment warning at vga_blue.v(116): truncated value with size 32 to match size of target (11)" {  } { { "../src/vga_blue.v" "" { Text "D:/RedLogic/RCII_samples/VGA_BLUE/src/vga_blue.v" 116 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 vga_blue.v(118) " "Warning: Verilog HDL assignment warning at vga_blue.v(118): truncated value with size 32 to match size of target (11)" {  } { { "../src/vga_blue.v" "" { Text "D:/RedLogic/RCII_samples/VGA_BLUE/src/vga_blue.v" 118 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 vga_blue.v(123) " "Warning: Verilog HDL assignment warning at vga_blue.v(123): truncated value with size 32 to match size of target (1)" {  } { { "../src/vga_blue.v" "" { Text "D:/RedLogic/RCII_samples/VGA_BLUE/src/vga_blue.v" 123 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 vga_blue.v(125) " "Warning: Verilog HDL assignment warning at vga_blue.v(125): truncated value with size 32 to match size of target (1)" {  } { { "../src/vga_blue.v" "" { Text "D:/RedLogic/RCII_samples/VGA_BLUE/src/vga_blue.v" 125 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 vga_blue.v(127) " "Warning: Verilog HDL assignment warning at vga_blue.v(127): truncated value with size 32 to match size of target (1)" {  } { { "../src/vga_blue.v" "" { Text "D:/RedLogic/RCII_samples/VGA_BLUE/src/vga_blue.v" 127 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 vga_blue.v(132) " "Warning: Verilog HDL assignment warning at vga_blue.v(132): truncated value with size 32 to match size of target (1)" {  } { { "../src/vga_blue.v" "" { Text "D:/RedLogic/RCII_samples/VGA_BLUE/src/vga_blue.v" 132 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 vga_blue.v(134) " "Warning: Verilog HDL assignment warning at vga_blue.v(134): truncated value with size 32 to match size of target (1)" {  } { { "../src/vga_blue.v" "" { Text "D:/RedLogic/RCII_samples/VGA_BLUE/src/vga_blue.v" 134 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 vga_blue.v(136) " "Warning: Verilog HDL assignment warning at vga_blue.v(136): truncated value with size 32 to match size of target (1)" {  } { { "../src/vga_blue.v" "" { Text "D:/RedLogic/RCII_samples/VGA_BLUE/src/vga_blue.v" 136 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "VGA_PLL.v 1 1 " "Info: Using design file VGA_PLL.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 VGA_PLL " "Info: Found entity 1: VGA_PLL" {  } { { "VGA_PLL.v" "" { Text "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/VGA_PLL.v" 42 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "VGA_PLL VGA_PLL:inst4 " "Info: Elaborating entity \"VGA_PLL\" for hierarchy \"VGA_PLL:inst4\"" {  } { { "../Src/BlueScreen.bdf" "inst4" { Schematic "D:/RedLogic/RCII_samples/VGA_BLUE/Src/BlueScreen.bdf" { { -32 336 592 128 "inst4" "" } } } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 363 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll VGA_PLL:inst4\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"VGA_PLL:inst4\|altpll:altpll_component\"" {  } { { "VGA_PLL.v" "altpll_component" { Text "D:/RedLogic/RCII_samples/VGA_BLUE/Proj/VGA_PLL.v" 89 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_RGB\[1\] GND " "Warning: Pin \"VGA_RGB\[1\]\" stuck at GND" {  } { { "../Src/BlueScreen.bdf" "" { Schematic "D:/RedLogic/RCII_samples/VGA_BLUE/Src/BlueScreen.bdf" { { 272 608 784 288 "VGA_RGB\[2..0\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_RGB\[0\] GND " "Warning: Pin \"VGA_RGB\[0\]\" stuck at GND" {  } { { "../Src/BlueScreen.bdf" "" { Schematic "D:/RedLogic/RCII_samples/VGA_BLUE/Src/BlueScreen.bdf" { { 272 608 784 288 "VGA_RGB\[2..0\]" "" } } } }  } 0}  } {  } 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "../src/vga_blue.v" "" { Text "D:/RedLogic/RCII_samples/VGA_BLUE/src/vga_blue.v" 88 -1 0 } } { "../src/vga_blue.v" "" { Text "D:/RedLogic/RCII_samples/VGA_BLUE/src/vga_blue.v" 65 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "49 " "Info: Implemented 49 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "5 " "Info: Implemented 5 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "41 " "Info: Implemented 41 logic cells" {  } {  } 0} { "Info" "ISCL_SCL_TM_PLLS" "1 " "Info: Implemented 1 ClockLock PLLs" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 32 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 32 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jun 27 23:33:41 2005 " "Info: Processing ended: Mon Jun 27 23:33:41 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}