📄 colorbar.map.rpt
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; ENABLE0_COUNTER ; L0 ; Untyped ;
; ENABLE1_COUNTER ; L0 ; Untyped ;
; CHARGE_PUMP_CURRENT ; 2 ; Untyped ;
; LOOP_FILTER_R ; 1.000000 ; Untyped ;
; LOOP_FILTER_C ; 5 ; Untyped ;
; VCO_POST_SCALE ; 0 ; Untyped ;
; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ;
; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ;
; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ;
; INTENDED_DEVICE_FAMILY ; Cyclone ; Untyped ;
; PORT_CLKENA0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLKENA1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLKENA2 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLKENA3 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLKENA4 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLKENA5 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLK0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLK1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLK2 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLK3 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLKBAD0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLKBAD1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLK0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLK1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLK2 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLK3 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLK4 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLK5 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCANDATA ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCANDATAOUT ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCANDONE ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_ACTIVECLOCK ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLKLOSS ; PORT_CONNECTIVITY ; Untyped ;
; PORT_INCLK1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_INCLK0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_FBIN ; PORT_CONNECTIVITY ; Untyped ;
; PORT_PLLENA ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLKSWITCH ; PORT_CONNECTIVITY ; Untyped ;
; PORT_ARESET ; PORT_CONNECTIVITY ; Untyped ;
; PORT_PFDENA ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCANCLK ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCANACLR ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCANREAD ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCANWRITE ; PORT_CONNECTIVITY ; Untyped ;
; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ;
; M_TEST_SOURCE ; 5 ; Untyped ;
; C0_TEST_SOURCE ; 5 ; Untyped ;
; C1_TEST_SOURCE ; 5 ; Untyped ;
; C2_TEST_SOURCE ; 5 ; Untyped ;
; C3_TEST_SOURCE ; 5 ; Untyped ;
; C4_TEST_SOURCE ; 5 ; Untyped ;
; C5_TEST_SOURCE ; 5 ; Untyped ;
; DEVICE_FAMILY ; Cyclone ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+-------------------------------+-------------------+--------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/RedLogic/RCII_samples/VGA_BLUE/Proj/ColorBar.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Mon Jun 27 23:33:38 2005
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ColorBar -c ColorBar
Warning: Verilog Module Declaration warning at vga_blue.v(63): ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module "vga_blue"
Info: Found 1 design units, including 1 entities, in source file ../src/vga_blue.v
Info: Found entity 1: vga_blue
Info: Found 1 design units, including 1 entities, in source file ../Src/BlueScreen.bdf
Info: Found entity 1: BlueScreen
Info: Elaborating entity "BlueScreen" for the top level hierarchy
Warning: Can't find a definition for parameter H_PIXELS -- assuming 32'b00000000000000000000001100100110 was intended to be a quoted string
Warning: Can't find a definition for parameter H_FRONTPORCH -- assuming 32'b00000000000000000000000000100101 was intended to be a quoted string
Warning: Can't find a definition for parameter H_SYNCTIME -- assuming 32'b00000000000000000000000010000000 was intended to be a quoted string
Warning: Can't find a definition for parameter H_BACKPORCH -- assuming 32'b00000000000000000000000001010101 was intended to be a quoted string
Warning: Can't find a definition for parameter H_SYNCSTART -- assuming 32'b00000000000000000000001101001011 was intended to be a quoted string
Warning: Can't find a definition for parameter H_SYNCEND -- assuming 32'b00000000000000000000001111001011 was intended to be a quoted string
Warning: Can't find a definition for parameter H_PERIOD -- assuming 32'b00000000000000000000010000100000 was intended to be a quoted string
Warning: Can't find a definition for parameter V_LINES -- assuming 32'b00000000000000000000001001011100 was intended to be a quoted string
Warning: Can't find a definition for parameter V_SYNCTIME -- assuming 32'b00000000000000000000000000000100 was intended to be a quoted string
Warning: Can't find a definition for parameter V_BACKPORCH -- assuming 32'b00000000000000000000000000010101 was intended to be a quoted string
Warning: Can't find a definition for parameter V_SYNCSTART -- assuming 32'b00000000000000000000001001011011 was intended to be a quoted string
Warning: Can't find a definition for parameter V_SYNCEND -- assuming 32'b00000000000000000000001001011111 was intended to be a quoted string
Warning: Can't find a definition for parameter V_PERIOD -- assuming 32'b00000000000000000000001001110100 was intended to be a quoted string
Info: Elaborating entity "vga_blue" for hierarchy "vga_blue:inst"
Warning: Verilog HDL assignment warning at vga_blue.v(93): truncated value with size 32 to match size of target (11)
Warning: Verilog HDL assignment warning at vga_blue.v(95): truncated value with size 32 to match size of target (11)
Warning: Verilog HDL assignment warning at vga_blue.v(97): truncated value with size 32 to match size of target (11)
Warning: Verilog HDL assignment warning at vga_blue.v(102): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at vga_blue.v(104): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at vga_blue.v(106): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at vga_blue.v(114): truncated value with size 32 to match size of target (11)
Warning: Verilog HDL assignment warning at vga_blue.v(116): truncated value with size 32 to match size of target (11)
Warning: Verilog HDL assignment warning at vga_blue.v(118): truncated value with size 32 to match size of target (11)
Warning: Verilog HDL assignment warning at vga_blue.v(123): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at vga_blue.v(125): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at vga_blue.v(127): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at vga_blue.v(132): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at vga_blue.v(134): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at vga_blue.v(136): truncated value with size 32 to match size of target (1)
Info: Using design file VGA_PLL.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: VGA_PLL
Info: Elaborating entity "VGA_PLL" for hierarchy "VGA_PLL:inst4"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altpll.tdf
Info: Found entity 1: altpll
Info: Elaborating entity "altpll" for hierarchy "VGA_PLL:inst4|altpll:altpll_component"
Warning: Output pins are stuck at VCC or GND
Warning: Pin "VGA_RGB[1]" stuck at GND
Warning: Pin "VGA_RGB[0]" stuck at GND
Info: Registers with preset signals will power-up high
Info: Implemented 49 device resources after synthesis - the final resource count might be different
Info: Implemented 2 input pins
Info: Implemented 5 output pins
Info: Implemented 41 logic cells
Info: Implemented 1 ClockLock PLLs
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 32 warnings
Info: Processing ended: Mon Jun 27 23:33:41 2005
Info: Elapsed time: 00:00:04
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