colorbar.map.qmsg

this a sample about the VGA COLORBAR,the function of this code is show eight different colour in VGA

{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 vga_vl.v(128) " "Warning: Verilog HDL assignment warning at vga_vl.v(128): truncated value with size 32 to match size of target (1)" {  } { { "../src/vga_vl.v" "" { Text "D:/RedLogic/RCII_samples/VGA_COLORBAR/src/vga_vl.v" 128 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 vga_vl.v(130) " "Warning: Verilog HDL assignment warning at vga_vl.v(130): truncated value with size 32 to match size of target (1)" {  } { { "../src/vga_vl.v" "" { Text "D:/RedLogic/RCII_samples/VGA_COLORBAR/src/vga_vl.v" 130 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 vga_vl.v(135) " "Warning: Verilog HDL assignment warning at vga_vl.v(135): truncated value with size 32 to match size of target (1)" {  } { { "../src/vga_vl.v" "" { Text "D:/RedLogic/RCII_samples/VGA_COLORBAR/src/vga_vl.v" 135 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 vga_vl.v(137) " "Warning: Verilog HDL assignment warning at vga_vl.v(137): truncated value with size 32 to match size of target (1)" {  } { { "../src/vga_vl.v" "" { Text "D:/RedLogic/RCII_samples/VGA_COLORBAR/src/vga_vl.v" 137 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 vga_vl.v(139) " "Warning: Verilog HDL assignment warning at vga_vl.v(139): truncated value with size 32 to match size of target (1)" {  } { { "../src/vga_vl.v" "" { Text "D:/RedLogic/RCII_samples/VGA_COLORBAR/src/vga_vl.v" 139 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 vga_vl.v(144) " "Warning: Verilog HDL assignment warning at vga_vl.v(144): truncated value with size 32 to match size of target (3)" {  } { { "../src/vga_vl.v" "" { Text "D:/RedLogic/RCII_samples/VGA_COLORBAR/src/vga_vl.v" 144 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 vga_vl.v(149) " "Warning: Verilog HDL assignment warning at vga_vl.v(149): truncated value with size 32 to match size of target (3)" {  } { { "../src/vga_vl.v" "" { Text "D:/RedLogic/RCII_samples/VGA_COLORBAR/src/vga_vl.v" 149 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 vga_vl.v(152) " "Warning: Verilog HDL assignment warning at vga_vl.v(152): truncated value with size 32 to match size of target (3)" {  } { { "../src/vga_vl.v" "" { Text "D:/RedLogic/RCII_samples/VGA_COLORBAR/src/vga_vl.v" 152 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 vga_vl.v(155) " "Warning: Verilog HDL assignment warning at vga_vl.v(155): truncated value with size 32 to match size of target (3)" {  } { { "../src/vga_vl.v" "" { Text "D:/RedLogic/RCII_samples/VGA_COLORBAR/src/vga_vl.v" 155 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 vga_vl.v(158) " "Warning: Verilog HDL assignment warning at vga_vl.v(158): truncated value with size 32 to match size of target (3)" {  } { { "../src/vga_vl.v" "" { Text "D:/RedLogic/RCII_samples/VGA_COLORBAR/src/vga_vl.v" 158 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 vga_vl.v(161) " "Warning: Verilog HDL assignment warning at vga_vl.v(161): truncated value with size 32 to match size of target (3)" {  } { { "../src/vga_vl.v" "" { Text "D:/RedLogic/RCII_samples/VGA_COLORBAR/src/vga_vl.v" 161 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 vga_vl.v(164) " "Warning: Verilog HDL assignment warning at vga_vl.v(164): truncated value with size 32 to match size of target (3)" {  } { { "../src/vga_vl.v" "" { Text "D:/RedLogic/RCII_samples/VGA_COLORBAR/src/vga_vl.v" 164 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 vga_vl.v(167) " "Warning: Verilog HDL assignment warning at vga_vl.v(167): truncated value with size 32 to match size of target (3)" {  } { { "../src/vga_vl.v" "" { Text "D:/RedLogic/RCII_samples/VGA_COLORBAR/src/vga_vl.v" 167 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 vga_vl.v(169) " "Warning: Verilog HDL assignment warning at vga_vl.v(169): truncated value with size 32 to match size of target (3)" {  } { { "../src/vga_vl.v" "" { Text "D:/RedLogic/RCII_samples/VGA_COLORBAR/src/vga_vl.v" 169 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 vga_vl.v(174) " "Warning: Verilog HDL assignment warning at vga_vl.v(174): truncated value with size 32 to match size of target (3)" {  } { { "../src/vga_vl.v" "" { Text "D:/RedLogic/RCII_samples/VGA_COLORBAR/src/vga_vl.v" 174 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 vga_vl.v(177) " "Warning: Verilog HDL assignment warning at vga_vl.v(177): truncated value with size 32 to match size of target (3)" {  } { { "../src/vga_vl.v" "" { Text "D:/RedLogic/RCII_samples/VGA_COLORBAR/src/vga_vl.v" 177 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 vga_vl.v(180) " "Warning: Verilog HDL assignment warning at vga_vl.v(180): truncated value with size 32 to match size of target (3)" {  } { { "../src/vga_vl.v" "" { Text "D:/RedLogic/RCII_samples/VGA_COLORBAR/src/vga_vl.v" 180 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 vga_vl.v(183) " "Warning: Verilog HDL assignment warning at vga_vl.v(183): truncated value with size 32 to match size of target (3)" {  } { { "../src/vga_vl.v" "" { Text "D:/RedLogic/RCII_samples/VGA_COLORBAR/src/vga_vl.v" 183 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 vga_vl.v(186) " "Warning: Verilog HDL assignment warning at vga_vl.v(186): truncated value with size 32 to match size of target (3)" {  } { { "../src/vga_vl.v" "" { Text "D:/RedLogic/RCII_samples/VGA_COLORBAR/src/vga_vl.v" 186 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 vga_vl.v(189) " "Warning: Verilog HDL assignment warning at vga_vl.v(189): truncated value with size 32 to match size of target (3)" {  } { { "../src/vga_vl.v" "" { Text "D:/RedLogic/RCII_samples/VGA_COLORBAR/src/vga_vl.v" 189 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 vga_vl.v(192) " "Warning: Verilog HDL assignment warning at vga_vl.v(192): truncated value with size 32 to match size of target (3)" {  } { { "../src/vga_vl.v" "" { Text "D:/RedLogic/RCII_samples/VGA_COLORBAR/src/vga_vl.v" 192 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 vga_vl.v(194) " "Warning: Verilog HDL assignment warning at vga_vl.v(194): truncated value with size 32 to match size of target (3)" {  } { { "../src/vga_vl.v" "" { Text "D:/RedLogic/RCII_samples/VGA_COLORBAR/src/vga_vl.v" 194 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "VGA_PLL.v 1 1 " "Info: Using design file VGA_PLL.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 VGA_PLL " "Info: Found entity 1: VGA_PLL" {  } { { "VGA_PLL.v" "" { Text "D:/RedLogic/RCII_samples/VGA_COLORBAR/Proj/VGA_PLL.v" 42 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "VGA_PLL VGA_PLL:inst4 " "Info: Elaborating entity \"VGA_PLL\" for hierarchy \"VGA_PLL:inst4\"" {  } { { "../Src/ColorBar.bdf" "inst4" { Schematic "D:/RedLogic/RCII_samples/VGA_COLORBAR/Src/ColorBar.bdf" { { -32 336 592 128 "inst4" "" } } } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 363 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll VGA_PLL:inst4\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"VGA_PLL:inst4\|altpll:altpll_component\"" {  } { { "VGA_PLL.v" "altpll_component" { Text "D:/RedLogic/RCII_samples/VGA_COLORBAR/Proj/VGA_PLL.v" 89 -1 0 } }  } 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "../src/vga_vl.v" "" { Text "D:/RedLogic/RCII_samples/VGA_COLORBAR/src/vga_vl.v" 91 -1 0 } } { "../src/vga_vl.v" "" { Text "D:/RedLogic/RCII_samples/VGA_COLORBAR/src/vga_vl.v" 67 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "73 " "Info: Implemented 73 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "5 " "Info: Implemented 5 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "65 " "Info: Implemented 65 logic cells" {  } {  } 0} { "Info" "ISCL_SCL_TM_PLLS" "1 " "Info: Implemented 1 ClockLock PLLs" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 45 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 45 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jun 27 23:34:29 2005 " "Info: Processing ended: Mon Jun 27 23:34:29 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}