colorbar.fit.qmsg

this a sample about the VGA COLORBAR,the function of this code is show eight different colour in VGA

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jun 27 23:34:32 2005 " "Info: Processing started: Mon Jun 27 23:34:32 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off ColorBar -c ColorBar " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off ColorBar -c ColorBar" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "ColorBar EP1C12Q240C8 " "Info: Selected device EP1C12Q240C8 for design \"ColorBar\"" {  } {  } 0}
{ "Info" "ICUT_CUT_YGR_PLL_CAN_ACHIEVE_RATIO_AND_PHASE_SHIFT" "VGA_PLL:inst4\|altpll:altpll_component\|pll " "Info: Implementing parameter values for PLL \"VGA_PLL:inst4\|altpll:altpll_component\|pll\"" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "VGA_PLL:inst4\|altpll:altpll_component\|_clk0 4 5 0 0 " "Info: Implementing clock multiplication of 4, clock division of 5, and phase shift of 0 degrees (0 ps) for VGA_PLL:inst4\|altpll:altpll_component\|_clk0 port" {  } {  } 0}  } { { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } } { "VGA_PLL.v" "" { Text "D:/RedLogic/RCII_samples/VGA_COLORBAR/Proj/VGA_PLL.v" 89 -1 0 } } { "../Src/ColorBar.bdf" "" { Schematic "D:/RedLogic/RCII_samples/VGA_COLORBAR/Src/ColorBar.bdf" { { -32 336 592 128 "inst4" "" } } } }  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6Q240C8 " "Info: Device EP1C6Q240C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_PLL_CLK_PROMOTION" "" "Info: Promoted PLL clock signals" { { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK_USER" "VGA_PLL:inst4\|altpll:altpll_component\|_clk0 " "Info: Promoted signal \"VGA_PLL:inst4\|altpll:altpll_component\|_clk0\" to use global clock (user assigned)" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "VGA_PLL:inst4\|altpll:altpll_component\|_clk0" } { 0 "VGA_PLL:inst4\|altpll:altpll_component\|_clk0" } } } } { "../Src/ColorBar.bdf" "" { Schematic "D:/RedLogic/RCII_samples/VGA_COLORBAR/Src/ColorBar.bdf" { { -32 336 592 128 "inst4" "" } } } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } } { "D:/RedLogic/RCII_samples/VGA_COLORBAR/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_COLORBAR/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_COLORBAR/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_COLORBAR/Proj/" "" "" { VGA_PLL:inst4|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "D:/RedLogic/RCII_samples/VGA_COLORBAR/Proj/ColorBar.fld" "" { Floorplan "D:/RedLogic/RCII_samples/VGA_COLORBAR/Proj/ColorBar.fld" "" "" { VGA_PLL:inst4|altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "PLL Placement Operation " "Info: Completed PLL Placement Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "vga_vl:inst\|hsyncint Global clock " "Info: Automatically promoted some destinations of signal \"vga_vl:inst\|hsyncint\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "VGA_HS " "Info: Destination \"VGA_HS\" may be non-global or may not use global clock" {  } { { "../Src/ColorBar.bdf" "" { Schematic "D:/RedLogic/RCII_samples/VGA_COLORBAR/Src/ColorBar.bdf" { { 240 608 784 256 "VGA_HS" "" } } } }  } 0}  } { { "../src/vga_vl.v" "" { Text "D:/RedLogic/RCII_samples/VGA_COLORBAR/src/vga_vl.v" 91 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "rst Global clock in PIN 131 " "Info: Automatically promoted signal \"rst\" to use Global clock in PIN 131" {  } { { "../Src/ColorBar.bdf" "" { Schematic "D:/RedLogic/RCII_samples/VGA_COLORBAR/Src/ColorBar.bdf" { { 240 104 272 256 "rst" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.582 ns register register " "Info: Estimated most critical path is register to register delay of 3.582 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga_vl:inst\|vcnt\[3\] 1 REG LAB_X30_Y15 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X30_Y15; Fanout = 5; REG Node = 'vga_vl:inst\|vcnt\[3\]'" {  } { { "D:/RedLogic/RCII_samples/VGA_COLORBAR/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_COLORBAR/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_COLORBAR/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_COLORBAR/Proj/" "" "" { vga_vl:inst|vcnt[3] } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "D:/RedLogic/RCII_samples/VGA_COLORBAR/src/vga_vl.v" 90 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.852 ns) + CELL(0.590 ns) 1.442 ns vga_vl:inst\|always4~149 2 COMB LAB_X29_Y14 2 " "Info: 2: + IC(0.852 ns) + CELL(0.590 ns) = 1.442 ns; Loc. = LAB_X29_Y14; Fanout = 2; COMB Node = 'vga_vl:inst\|always4~149'" {  } { { "D:/RedLogic/RCII_samples/VGA_COLORBAR/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_COLORBAR/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_COLORBAR/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_COLORBAR/Proj/" "" "1.442 ns" { vga_vl:inst|vcnt[3] vga_vl:inst|always4~149 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.372 ns) + CELL(0.292 ns) 2.106 ns vga_vl:inst\|always4~152 3 COMB LAB_X29_Y14 1 " "Info: 3: + IC(0.372 ns) + CELL(0.292 ns) = 2.106 ns; Loc. = LAB_X29_Y14; Fanout = 1; COMB Node = 'vga_vl:inst\|always4~152'" {  } { { "D:/RedLogic/RCII_samples/VGA_COLORBAR/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_COLORBAR/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_COLORBAR/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_COLORBAR/Proj/" "" "0.664 ns" { vga_vl:inst|always4~149 vga_vl:inst|always4~152 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.114 ns) 2.770 ns vga_vl:inst\|always4~153 4 COMB LAB_X29_Y14 1 " "Info: 4: + IC(0.550 ns) + CELL(0.114 ns) = 2.770 ns; Loc. = LAB_X29_Y14; Fanout = 1; COMB Node = 'vga_vl:inst\|always4~153'" {  } { { "D:/RedLogic/RCII_samples/VGA_COLORBAR/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_COLORBAR/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_COLORBAR/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_COLORBAR/Proj/" "" "0.664 ns" { vga_vl:inst|always4~152 vga_vl:inst|always4~153 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.074 ns) + CELL(0.738 ns) 3.582 ns vga_vl:inst\|enable 5 REG LAB_X29_Y14 5 " "Info: 5: + IC(0.074 ns) + CELL(0.738 ns) = 3.582 ns; Loc. = LAB_X29_Y14; Fanout = 5; REG Node = 'vga_vl:inst\|enable'" {  } { { "D:/RedLogic/RCII_samples/VGA_COLORBAR/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_COLORBAR/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_COLORBAR/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_COLORBAR/Proj/" "" "0.812 ns" { vga_vl:inst|always4~153 vga_vl:inst|enable } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "D:/RedLogic/RCII_samples/VGA_COLORBAR/src/vga_vl.v" 91 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.734 ns 48.41 % " "Info: Total cell delay = 1.734 ns ( 48.41 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.848 ns 51.59 % " "Info: Total interconnect delay = 1.848 ns ( 51.59 % )" {  } {  } 0}  } { { "D:/RedLogic/RCII_samples/VGA_COLORBAR/Proj/db/ColorBar_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/VGA_COLORBAR/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/VGA_COLORBAR/Proj/db/ColorBar.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/VGA_COLORBAR/Proj/" "" "3.582 ns" { vga_vl:inst|vcnt[3] vga_vl:inst|always4~149 vga_vl:inst|always4~152 vga_vl:inst|always4~153 vga_vl:inst|enable } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jun 27 23:34:42 2005 " "Info: Processing ended: Mon Jun 27 23:34:42 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" {  } {  } 0}  } {  } 0}