fpga2pc.tan.qmsg

this is a sample about usb in transmission,it s default installation is D:RedLogicRCII_samples, and

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\] register sld_hub:sld_hub_inst\|hub_tdo 105.35 MHz 9.492 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 105.35 MHz between source register \"sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\]\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo\" (period= 9.492 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.485 ns + Longest register register " "Info: + Longest register to register delay is 4.485 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\] 1 REG LC_X36_Y11_N4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X36_Y11_N4; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\]'" {  } { { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } "NODE_NAME" } "" } } { "sld_rom_sr.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.594 ns) + CELL(0.590 ns) 2.184 ns sld_hub:sld_hub_inst\|hub_tdo~277 2 COMB LC_X30_Y11_N4 1 " "Info: 2: + IC(1.594 ns) + CELL(0.590 ns) = 2.184 ns; Loc. = LC_X30_Y11_N4; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~277'" {  } { { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "2.184 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo~277 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.688 ns) + CELL(0.442 ns) 3.314 ns sld_hub:sld_hub_inst\|hub_tdo~278 3 COMB LC_X31_Y11_N9 1 " "Info: 3: + IC(0.688 ns) + CELL(0.442 ns) = 3.314 ns; Loc. = LC_X31_Y11_N9; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~278'" {  } { { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "1.130 ns" { sld_hub:sld_hub_inst|hub_tdo~277 sld_hub:sld_hub_inst|hub_tdo~278 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.433 ns) + CELL(0.738 ns) 4.485 ns sld_hub:sld_hub_inst\|hub_tdo 4 REG LC_X31_Y11_N6 0 " "Info: 4: + IC(0.433 ns) + CELL(0.738 ns) = 4.485 ns; Loc. = LC_X31_Y11_N6; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "1.171 ns" { sld_hub:sld_hub_inst|hub_tdo~278 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.770 ns 39.46 % " "Info: Total cell delay = 1.770 ns ( 39.46 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.715 ns 60.54 % " "Info: Total interconnect delay = 2.715 ns ( 60.54 % )" {  } {  } 0}  } { { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "4.485 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo~277 sld_hub:sld_hub_inst|hub_tdo~278 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.485 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo~277 sld_hub:sld_hub_inst|hub_tdo~278 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.594ns 0.688ns 0.433ns } { 0.000ns 0.590ns 0.442ns 0.738ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.294 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.294 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y13_N1 230 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y13_N1; Fanout = 230; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.583 ns) + CELL(0.711 ns) 5.294 ns sld_hub:sld_hub_inst\|hub_tdo 2 REG LC_X31_Y11_N6 0 " "Info: 2: + IC(4.583 ns) + CELL(0.711 ns) = 5.294 ns; Loc. = LC_X31_Y11_N6; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "5.294 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 13.43 % " "Info: Total cell delay = 0.711 ns ( 13.43 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.583 ns 86.57 % " "Info: Total interconnect delay = 4.583 ns ( 86.57 % )" {  } {  } 0}  } { { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "5.294 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.294 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.583ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 5.294 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 5.294 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y13_N1 230 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y13_N1; Fanout = 230; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.583 ns) + CELL(0.711 ns) 5.294 ns sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\] 2 REG LC_X36_Y11_N4 1 " "Info: 2: + IC(4.583 ns) + CELL(0.711 ns) = 5.294 ns; Loc. = LC_X36_Y11_N4; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\]'" {  } { { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "5.294 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } "NODE_NAME" } "" } } { "sld_rom_sr.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 13.43 % " "Info: Total cell delay = 0.711 ns ( 13.43 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.583 ns 86.57 % " "Info: Total interconnect delay = 4.583 ns ( 86.57 % )" {  } {  } 0}  } { { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "5.294 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.294 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } { 0.000ns 4.583ns } { 0.000ns 0.711ns } } }  } 0}  } { { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "5.294 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.294 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.583ns } { 0.000ns 0.711ns } } } { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "5.294 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.294 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } { 0.000ns 4.583ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "sld_rom_sr.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "sld_rom_sr.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 33 -1 0 } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0}  } { { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "4.485 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo~277 sld_hub:sld_hub_inst|hub_tdo~278 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.485 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo~277 sld_hub:sld_hub_inst|hub_tdo~278 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.594ns 0.688ns 0.433ns } { 0.000ns 0.590ns 0.442ns 0.738ns } } } { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "5.294 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.294 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.583ns } { 0.000ns 0.711ns } } } { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "5.294 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.294 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } { 0.000ns 4.583ns } { 0.000ns 0.711ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "sld_hub:sld_hub_inst\|lpm_decode:instruction_decoder\|decode_9ie:auto_generated\|dffe1a\[1\] altera_internal_jtag altera_internal_jtag~TCKUTAP 1.043 ns register " "Info: tsu for register \"sld_hub:sld_hub_inst\|lpm_decode:instruction_decoder\|decode_9ie:auto_generated\|dffe1a\[1\]\" (data pin = \"altera_internal_jtag\", clock pin = \"altera_internal_jtag~TCKUTAP\") is 1.043 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.298 ns + Longest pin register " "Info: + Longest pin to register delay is 6.298 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag 1 PIN JTAG_X1_Y13_N1 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y13_N1; Fanout = 9; PIN Node = 'altera_internal_jtag'" {  } { { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "" { altera_internal_jtag } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.590 ns) + CELL(0.590 ns) 4.180 ns sld_hub:sld_hub_inst\|comb~67 2 COMB LC_X30_Y11_N7 5 " "Info: 2: + IC(3.590 ns) + CELL(0.590 ns) = 4.180 ns; Loc. = LC_X30_Y11_N7; Fanout = 5; COMB Node = 'sld_hub:sld_hub_inst\|comb~67'" {  } { { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "4.180 ns" { altera_internal_jtag sld_hub:sld_hub_inst|comb~67 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.251 ns) + CELL(0.867 ns) 6.298 ns sld_hub:sld_hub_inst\|lpm_decode:instruction_decoder\|decode_9ie:auto_generated\|dffe1a\[1\] 3 REG LC_X31_Y10_N4 2 " "Info: 3: + IC(1.251 ns) + CELL(0.867 ns) = 6.298 ns; Loc. = LC_X31_Y10_N4; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|lpm_decode:instruction_decoder\|decode_9ie:auto_generated\|dffe1a\[1\]'" {  } { { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "2.118 ns" { sld_hub:sld_hub_inst|comb~67 sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated|dffe1a[1] } "NODE_NAME" } "" } } { "db/decode_9ie.tdf" "" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/decode_9ie.tdf" 32 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.457 ns 23.13 % " "Info: Total cell delay = 1.457 ns ( 23.13 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.841 ns 76.87 % " "Info: Total interconnect delay = 4.841 ns ( 76.87 % )" {  } {  } 0}  } { { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "6.298 ns" { altera_internal_jtag sld_hub:sld_hub_inst|comb~67 sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated|dffe1a[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.298 ns" { altera_internal_jtag sld_hub:sld_hub_inst|comb~67 sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated|dffe1a[1] } { 0.000ns 3.590ns 1.251ns } { 0.000ns 0.590ns 0.867ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "db/decode_9ie.tdf" "" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/decode_9ie.tdf" 32 8 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.292 ns - Shortest register " "Info: - Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.292 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y13_N1 230 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y13_N1; Fanout = 230; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.581 ns) + CELL(0.711 ns) 5.292 ns sld_hub:sld_hub_inst\|lpm_decode:instruction_decoder\|decode_9ie:auto_generated\|dffe1a\[1\] 2 REG LC_X31_Y10_N4 2 " "Info: 2: + IC(4.581 ns) + CELL(0.711 ns) = 5.292 ns; Loc. = LC_X31_Y10_N4; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|lpm_decode:instruction_decoder\|decode_9ie:auto_generated\|dffe1a\[1\]'" {  } { { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated|dffe1a[1] } "NODE_NAME" } "" } } { "db/decode_9ie.tdf" "" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/decode_9ie.tdf" 32 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 13.44 % " "Info: Total cell delay = 0.711 ns ( 13.44 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.581 ns 86.56 % " "Info: Total interconnect delay = 4.581 ns ( 86.56 % )" {  } {  } 0}  } { { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated|dffe1a[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated|dffe1a[1] } { 0.000ns 4.581ns } { 0.000ns 0.711ns } } }  } 0}  } { { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "6.298 ns" { altera_internal_jtag sld_hub:sld_hub_inst|comb~67 sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated|dffe1a[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.298 ns" { altera_internal_jtag sld_hub:sld_hub_inst|comb~67 sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated|dffe1a[1] } { 0.000ns 3.590ns 1.251ns } { 0.000ns 0.590ns 0.867ns } } } { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated|dffe1a[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated|dffe1a[1] } { 0.000ns 4.581ns } { 0.000ns 0.711ns } } }  } 0}