fpga2pc.tan.qmsg

this is a sample about usb in transmission,it s default installation is D:RedLogicRCII_samples, and

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clkin " "Info: Detected ripple clock \"clkin\" as buffer" {  } { { "../Src/fpga2pc.v" "" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 32 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkin" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_e29:auto_generated\|safe_q\[3\] register sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena 123.99 MHz 8.065 ns Internal " "Info: Clock \"clk\" has Internal fmax of 123.99 MHz between source register \"sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_e29:auto_generated\|safe_q\[3\]\" and destination register \"sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena\" (period= 8.065 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.804 ns + Longest register register " "Info: + Longest register to register delay is 7.804 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_e29:auto_generated\|safe_q\[3\] 1 REG LC_X27_Y9_N3 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X27_Y9_N3; Fanout = 4; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_e29:auto_generated\|safe_q\[3\]'" {  } { { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_e29:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "db/cntr_e29.tdf" "" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/cntr_e29.tdf" 120 8 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.210 ns) + CELL(0.442 ns) 1.652 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_compare:\\non_zero_sample_depth_gen:segment_addr_compare\|comptree:comparator\|cmpchain:cmp_end\|comptree:comp\|comptree:sub_comptree\|comptree:sub_comptree\|cmpchain:cmp_end\|aeb_out~61 2 COMB LC_X28_Y9_N5 1 " "Info: 2: + IC(1.210 ns) + CELL(0.442 ns) = 1.652 ns; Loc. = LC_X28_Y9_N5; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_compare:\\non_zero_sample_depth_gen:segment_addr_compare\|comptree:comparator\|cmpchain:cmp_end\|comptree:comp\|comptree:sub_comptree\|comptree:sub_comptree\|cmpchain:cmp_end\|aeb_out~61'" {  } { { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "1.652 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_e29:auto_generated|safe_q[3] sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~61 } "NODE_NAME" } "" } } { "cmpchain.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/cmpchain.tdf" 116 6 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.964 ns) + CELL(0.590 ns) 4.206 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_compare:\\non_zero_sample_depth_gen:segment_addr_compare\|comptree:comparator\|cmpchain:cmp_end\|comptree:comp\|comptree:sub_comptree\|comptree:sub_comptree\|cmpchain:cmp_end\|aeb_out~62 3 COMB LC_X28_Y9_N8 1 " "Info: 3: + IC(1.964 ns) + CELL(0.590 ns) = 4.206 ns; Loc. = LC_X28_Y9_N8; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_compare:\\non_zero_sample_depth_gen:segment_addr_compare\|comptree:comparator\|cmpchain:cmp_end\|comptree:comp\|comptree:sub_comptree\|comptree:sub_comptree\|cmpchain:cmp_end\|aeb_out~62'" {  } { { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "2.554 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~61 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~62 } "NODE_NAME" } "" } } { "cmpchain.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/cmpchain.tdf" 116 6 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.717 ns) + CELL(0.590 ns) 5.513 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_compare:\\non_zero_sample_depth_gen:segment_addr_compare\|comptree:comparator\|cmpchain:cmp_end\|comptree:comp\|comptree:sub_comptree\|comptree:sub_comptree\|cmpchain:cmp_end\|aeb_out~0 4 COMB LC_X28_Y9_N1 11 " "Info: 4: + IC(0.717 ns) + CELL(0.590 ns) = 5.513 ns; Loc. = LC_X28_Y9_N1; Fanout = 11; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_compare:\\non_zero_sample_depth_gen:segment_addr_compare\|comptree:comparator\|cmpchain:cmp_end\|comptree:comp\|comptree:sub_comptree\|comptree:sub_comptree\|cmpchain:cmp_end\|aeb_out~0'" {  } { { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "1.307 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~62 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~0 } "NODE_NAME" } "" } } { "cmpchain.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/cmpchain.tdf" 116 6 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.553 ns) + CELL(0.738 ns) 7.804 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena 5 REG LC_X29_Y8_N7 12 " "Info: 5: + IC(1.553 ns) + CELL(0.738 ns) = 7.804 ns; Loc. = LC_X29_Y8_N7; Fanout = 12; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena'" {  } { { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "2.291 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~0 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } "" } } { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1399 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.360 ns 30.24 % " "Info: Total cell delay = 2.360 ns ( 30.24 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.444 ns 69.76 % " "Info: Total interconnect delay = 5.444 ns ( 69.76 % )" {  } {  } 0}  } { { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "7.804 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_e29:auto_generated|safe_q[3] sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~61 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~62 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~0 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.804 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_e29:auto_generated|safe_q[3] sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~61 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~62 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~0 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } { 0.000ns 1.210ns 1.964ns 0.717ns 1.553ns } { 0.000ns 0.442ns 0.590ns 0.590ns 0.738ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 10.645 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 10.645 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 1; CLK Node = 'clk'" {  } { { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "" { clk } "NODE_NAME" } "" } } { "../Src/fpga2pc.v" "" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.015 ns) + CELL(0.935 ns) 6.419 ns clkin 2 REG LC_X8_Y13_N5 185 " "Info: 2: + IC(4.015 ns) + CELL(0.935 ns) = 6.419 ns; Loc. = LC_X8_Y13_N5; Fanout = 185; REG Node = 'clkin'" {  } { { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "4.950 ns" { clk clkin } "NODE_NAME" } "" } } { "../Src/fpga2pc.v" "" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 32 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.515 ns) + CELL(0.711 ns) 10.645 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena 3 REG LC_X29_Y8_N7 12 " "Info: 3: + IC(3.515 ns) + CELL(0.711 ns) = 10.645 ns; Loc. = LC_X29_Y8_N7; Fanout = 12; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena'" {  } { { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "4.226 ns" { clkin sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } "" } } { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1399 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 29.26 % " "Info: Total cell delay = 3.115 ns ( 29.26 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.530 ns 70.74 % " "Info: Total interconnect delay = 7.530 ns ( 70.74 % )" {  } {  } 0}  } { { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "10.645 ns" { clk clkin sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.645 ns" { clk clk~out0 clkin sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } { 0.000ns 0.000ns 4.015ns 3.515ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 10.645 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 10.645 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 1; CLK Node = 'clk'" {  } { { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "" { clk } "NODE_NAME" } "" } } { "../Src/fpga2pc.v" "" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.015 ns) + CELL(0.935 ns) 6.419 ns clkin 2 REG LC_X8_Y13_N5 185 " "Info: 2: + IC(4.015 ns) + CELL(0.935 ns) = 6.419 ns; Loc. = LC_X8_Y13_N5; Fanout = 185; REG Node = 'clkin'" {  } { { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "4.950 ns" { clk clkin } "NODE_NAME" } "" } } { "../Src/fpga2pc.v" "" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 32 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.515 ns) + CELL(0.711 ns) 10.645 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_e29:auto_generated\|safe_q\[3\] 3 REG LC_X27_Y9_N3 4 " "Info: 3: + IC(3.515 ns) + CELL(0.711 ns) = 10.645 ns; Loc. = LC_X27_Y9_N3; Fanout = 4; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_e29:auto_generated\|safe_q\[3\]'" {  } { { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "4.226 ns" { clkin sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_e29:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "db/cntr_e29.tdf" "" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/cntr_e29.tdf" 120 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 29.26 % " "Info: Total cell delay = 3.115 ns ( 29.26 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.530 ns 70.74 % " "Info: Total interconnect delay = 7.530 ns ( 70.74 % )" {  } {  } 0}  } { { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "10.645 ns" { clk clkin sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_e29:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.645 ns" { clk clk~out0 clkin sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_e29:auto_generated|safe_q[3] } { 0.000ns 0.000ns 4.015ns 3.515ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0}  } { { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "10.645 ns" { clk clkin sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.645 ns" { clk clk~out0 clkin sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } { 0.000ns 0.000ns 4.015ns 3.515ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "10.645 ns" { clk clkin sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_e29:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.645 ns" { clk clk~out0 clkin sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_e29:auto_generated|safe_q[3] } { 0.000ns 0.000ns 4.015ns 3.515ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "db/cntr_e29.tdf" "" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/cntr_e29.tdf" 120 8 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1399 -1 0 } }  } 0}  } { { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "7.804 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_e29:auto_generated|safe_q[3] sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~61 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~62 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~0 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.804 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_e29:auto_generated|safe_q[3] sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~61 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~62 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~0 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } { 0.000ns 1.210ns 1.964ns 0.717ns 1.553ns } { 0.000ns 0.442ns 0.590ns 0.590ns 0.738ns } } } { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "10.645 ns" { clk clkin sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.645 ns" { clk clk~out0 clkin sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } { 0.000ns 0.000ns 4.015ns 3.515ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/" "" "10.645 ns" { clk clkin sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_e29:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.645 ns" { clk clk~out0 clkin sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_e29:auto_generated|safe_q[3] } { 0.000ns 0.000ns 4.015ns 3.515ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0}