fpga2pc.hier_info

this is a sample about usb in transmission,it s default installation is D:RedLogicRCII_samples, and

|fpga2pc
rst => fifo_data[6]~reg0.PRESET
rst => fifo_data[5]~reg0.PRESET
rst => fifo_data[4]~reg0.PRESET
rst => fifo_data[3]~reg0.PRESET
rst => fifo_data[2]~reg0.PRESET
rst => fifo_data[1]~reg0.PRESET
rst => fifo_data[0]~reg0.PRESET
rst => fifo_wr~reg0.PRESET
rst => fifo_rd~reg0.PRESET
rst => fifo_data[7]~reg0.PRESET
rst => clkin.PRESET
rst => STATE~1.IN1
clk => clkin.CLK
fifo_wr <= fifo_wr~reg0.DB_MAX_OUTPUT_PORT_TYPE
fifo_rd <= fifo_rd~reg0.DB_MAX_OUTPUT_PORT_TYPE
fifo_data[0] <= fifo_data[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
fifo_data[1] <= fifo_data[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
fifo_data[2] <= fifo_data[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
fifo_data[3] <= fifo_data[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
fifo_data[4] <= fifo_data[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
fifo_data[5] <= fifo_data[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
fifo_data[6] <= fifo_data[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
fifo_data[7] <= fifo_data[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
fifo_pf => ~NO_FANOUT~
fifo_full => NEXT.WRITE_2.DATAB
fifo_full => NEXT.WRITE_1.DATAB
fifo_empty => ~NO_FANOUT~