fpga2pc.map.qmsg

this is a sample about usb in transmission,it s default installation is D:RedLogicRCII_samples, and

{ "Info" "ISGN_AE_SUCCESSFUL" "auto_signaltap_0 " "Info: Analysis and Synthesis generated SignalTap II or debug node instance \"auto_signaltap_0\"" { { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|fpga2pc\|clkin acq_clk " "Info: Source node \"\|fpga2pc\|clkin\" connects to port \"acq_clk\"" {  } { { "../Src/fpga2pc.v" "clkin" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 32 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|fpga2pc\|fifo_data\[0\] acq_trigger_in\[0\] " "Info: Source node \"\|fpga2pc\|fifo_data\[0\]\" connects to port \"acq_trigger_in\[0\]\"" {  } { { "../Src/fpga2pc.v" "fifo_data\[0\]" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|fpga2pc\|fifo_data\[0\] acq_data_in\[0\] " "Info: Source node \"\|fpga2pc\|fifo_data\[0\]\" connects to port \"acq_data_in\[0\]\"" {  } { { "../Src/fpga2pc.v" "fifo_data\[0\]" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|fpga2pc\|fifo_data\[1\] acq_trigger_in\[1\] " "Info: Source node \"\|fpga2pc\|fifo_data\[1\]\" connects to port \"acq_trigger_in\[1\]\"" {  } { { "../Src/fpga2pc.v" "fifo_data\[1\]" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|fpga2pc\|fifo_data\[1\] acq_data_in\[1\] " "Info: Source node \"\|fpga2pc\|fifo_data\[1\]\" connects to port \"acq_data_in\[1\]\"" {  } { { "../Src/fpga2pc.v" "fifo_data\[1\]" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|fpga2pc\|fifo_data\[2\] acq_trigger_in\[2\] " "Info: Source node \"\|fpga2pc\|fifo_data\[2\]\" connects to port \"acq_trigger_in\[2\]\"" {  } { { "../Src/fpga2pc.v" "fifo_data\[2\]" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|fpga2pc\|fifo_data\[2\] acq_data_in\[2\] " "Info: Source node \"\|fpga2pc\|fifo_data\[2\]\" connects to port \"acq_data_in\[2\]\"" {  } { { "../Src/fpga2pc.v" "fifo_data\[2\]" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|fpga2pc\|fifo_data\[3\] acq_trigger_in\[3\] " "Info: Source node \"\|fpga2pc\|fifo_data\[3\]\" connects to port \"acq_trigger_in\[3\]\"" {  } { { "../Src/fpga2pc.v" "fifo_data\[3\]" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|fpga2pc\|fifo_data\[3\] acq_data_in\[3\] " "Info: Source node \"\|fpga2pc\|fifo_data\[3\]\" connects to port \"acq_data_in\[3\]\"" {  } { { "../Src/fpga2pc.v" "fifo_data\[3\]" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|fpga2pc\|fifo_data\[4\] acq_trigger_in\[4\] " "Info: Source node \"\|fpga2pc\|fifo_data\[4\]\" connects to port \"acq_trigger_in\[4\]\"" {  } { { "../Src/fpga2pc.v" "fifo_data\[4\]" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|fpga2pc\|fifo_data\[4\] acq_data_in\[4\] " "Info: Source node \"\|fpga2pc\|fifo_data\[4\]\" connects to port \"acq_data_in\[4\]\"" {  } { { "../Src/fpga2pc.v" "fifo_data\[4\]" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|fpga2pc\|fifo_data\[5\] acq_trigger_in\[5\] " "Info: Source node \"\|fpga2pc\|fifo_data\[5\]\" connects to port \"acq_trigger_in\[5\]\"" {  } { { "../Src/fpga2pc.v" "fifo_data\[5\]" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|fpga2pc\|fifo_data\[5\] acq_data_in\[5\] " "Info: Source node \"\|fpga2pc\|fifo_data\[5\]\" connects to port \"acq_data_in\[5\]\"" {  } { { "../Src/fpga2pc.v" "fifo_data\[5\]" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|fpga2pc\|fifo_data\[6\] acq_trigger_in\[6\] " "Info: Source node \"\|fpga2pc\|fifo_data\[6\]\" connects to port \"acq_trigger_in\[6\]\"" {  } { { "../Src/fpga2pc.v" "fifo_data\[6\]" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|fpga2pc\|fifo_data\[6\] acq_data_in\[6\] " "Info: Source node \"\|fpga2pc\|fifo_data\[6\]\" connects to port \"acq_data_in\[6\]\"" {  } { { "../Src/fpga2pc.v" "fifo_data\[6\]" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|fpga2pc\|fifo_data\[7\] acq_trigger_in\[7\] " "Info: Source node \"\|fpga2pc\|fifo_data\[7\]\" connects to port \"acq_trigger_in\[7\]\"" {  } { { "../Src/fpga2pc.v" "fifo_data\[7\]" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|fpga2pc\|fifo_data\[7\] acq_data_in\[7\] " "Info: Source node \"\|fpga2pc\|fifo_data\[7\]\" connects to port \"acq_data_in\[7\]\"" {  } { { "../Src/fpga2pc.v" "fifo_data\[7\]" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|fpga2pc\|fifo_empty acq_trigger_in\[8\] " "Info: Source node \"\|fpga2pc\|fifo_empty\" connects to port \"acq_trigger_in\[8\]\"" {  } { { "../Src/fpga2pc.v" "fifo_empty" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 15 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|fpga2pc\|fifo_empty acq_data_in\[8\] " "Info: Source node \"\|fpga2pc\|fifo_empty\" connects to port \"acq_data_in\[8\]\"" {  } { { "../Src/fpga2pc.v" "fifo_empty" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 15 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|fpga2pc\|fifo_full acq_trigger_in\[9\] " "Info: Source node \"\|fpga2pc\|fifo_full\" connects to port \"acq_trigger_in\[9\]\"" {  } { { "../Src/fpga2pc.v" "fifo_full" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 15 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|fpga2pc\|fifo_full acq_data_in\[9\] " "Info: Source node \"\|fpga2pc\|fifo_full\" connects to port \"acq_data_in\[9\]\"" {  } { { "../Src/fpga2pc.v" "fifo_full" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 15 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|fpga2pc\|fifo_full trigger_in " "Info: Source node \"\|fpga2pc\|fifo_full\" connects to port \"trigger_in\"" {  } { { "../Src/fpga2pc.v" "fifo_full" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 15 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|fpga2pc\|fifo_pf acq_trigger_in\[10\] " "Info: Source node \"\|fpga2pc\|fifo_pf\" connects to port \"acq_trigger_in\[10\]\"" {  } { { "../Src/fpga2pc.v" "fifo_pf" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 15 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|fpga2pc\|fifo_pf acq_data_in\[10\] " "Info: Source node \"\|fpga2pc\|fifo_pf\" connects to port \"acq_data_in\[10\]\"" {  } { { "../Src/fpga2pc.v" "fifo_pf" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 15 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|fpga2pc\|fifo_rd acq_trigger_in\[11\] " "Info: Source node \"\|fpga2pc\|fifo_rd\" connects to port \"acq_trigger_in\[11\]\"" {  } { { "../Src/fpga2pc.v" "fifo_rd" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 19 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|fpga2pc\|fifo_rd acq_data_in\[11\] " "Info: Source node \"\|fpga2pc\|fifo_rd\" connects to port \"acq_data_in\[11\]\"" {  } { { "../Src/fpga2pc.v" "fifo_rd" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 19 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|fpga2pc\|fifo_wr acq_trigger_in\[12\] " "Info: Source node \"\|fpga2pc\|fifo_wr\" connects to port \"acq_trigger_in\[12\]\"" {  } { { "../Src/fpga2pc.v" "fifo_wr" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 18 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|fpga2pc\|fifo_wr acq_data_in\[12\] " "Info: Source node \"\|fpga2pc\|fifo_wr\" connects to port \"acq_data_in\[12\]\"" {  } { { "../Src/fpga2pc.v" "fifo_wr" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 18 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|fpga2pc\|rst acq_trigger_in\[13\] " "Info: Source node \"\|fpga2pc\|rst\" connects to port \"acq_trigger_in\[13\]\"" {  } { { "../Src/fpga2pc.v" "rst" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 13 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|fpga2pc\|rst acq_data_in\[13\] " "Info: Source node \"\|fpga2pc\|rst\" connects to port \"acq_data_in\[13\]\"" {  } { { "../Src/fpga2pc.v" "rst" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 13 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd 6 2 " "Info: Found 6 design units, including 2 entities, in source file c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 HUB_PACK " "Info: Found design unit 1: HUB_PACK" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 49 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 JTAG_PACK " "Info: Found design unit 2: JTAG_PACK" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 63 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 sld_hub-rtl " "Info: Found design unit 3: sld_hub-rtl" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 166 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 sld_jtag_state_machine-rtl " "Info: Found design unit 4: sld_jtag_state_machine-rtl" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 1012 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_hub " "Info: Found entity 1: sld_hub" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 99 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_jtag_state_machine " "Info: Found entity 2: sld_jtag_state_machine" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 997 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/lpm_decode.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_decode.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_decode " "Info: Found entity 1: lpm_decode" {  } { { "lpm_decode.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_decode.tdf" 62 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_9ie.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/decode_9ie.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_9ie " "Info: Found entity 1: decode_9ie" {  } { { "db/decode_9ie.tdf" "" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Proj/db/decode_9ie.tdf" 22 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_dffex-DFFEX " "Info: Found design unit 1: sld_dffex-DFFEX" {  } { { "sld_dffex.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 11 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_dffex " "Info: Found entity 1: sld_dffex" {  } { { "sld_dffex.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "fifo_rd~reg0 High " "Info: Power-up level of register \"fifo_rd~reg0\" is not specified -- using power-up level of High to minimize register" {  } { { "../Src/fpga2pc.v" "" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 19 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "fifo_rd~reg0 data_in VCC " "Warning: Reduced register \"fifo_rd~reg0\" with stuck data_in port to stuck value VCC" {  } { { "../Src/fpga2pc.v" "" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 19 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|fpga2pc\|STATE 3 0 " "Info: State machine \"\|fpga2pc\|STATE\" contains 3 states and 0 state bits" {  } { { "../Src/fpga2pc.v" "" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 33 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|fpga2pc\|STATE " "Info: Selected Auto state machine encoding method for state machine \"\|fpga2pc\|STATE\"" {  } { { "../Src/fpga2pc.v" "" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 33 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|fpga2pc\|STATE " "Info: Encoding result for state machine \"\|fpga2pc\|STATE\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "3 " "Info: Completed encoding using 3 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "STATE.IDLE " "Info: Encoded state bit \"STATE.IDLE\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "STATE.WRITE_2 " "Info: Encoded state bit \"STATE.WRITE_2\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "STATE.WRITE_1 " "Info: Encoded state bit \"STATE.WRITE_1\"" {  } { { "../Src/fpga2pc.v" "" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 33 -1 0 } }  } 0}  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|fpga2pc\|STATE.IDLE 000 " "Info: State \"\|fpga2pc\|STATE.IDLE\" uses code string \"000\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|fpga2pc\|STATE.WRITE_2 110 " "Info: State \"\|fpga2pc\|STATE.WRITE_2\" uses code string \"110\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|fpga2pc\|STATE.WRITE_1 101 " "Info: State \"\|fpga2pc\|STATE.WRITE_1\" uses code string \"101\"" {  } { { "../Src/fpga2pc.v" "" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 33 -1 0 } }  } 0}  } { { "../Src/fpga2pc.v" "" { Text "D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/USB_IN/Src/fpga2pc.v" 33 -1 0 } }  } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "8 " "Info: Ignored 8 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "8 " "Info: Ignored 8 SOFT buffer(s)" {  } {  } 0}  } {  } 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[11\] High " "Info: Power-up level of register \"sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[11\]\" is not specified -- using power-up level of High to minimize register" {  } { { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 437 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[11\] data_in VCC " "Warning: Reduced register \"sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[11\]\" with stuck data_in port to stuck value VCC" {  } { { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 437 -1 0 } }  } 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1\|holdff High " "Info: Power-up level of register \"sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1\|holdff\" is not specified -- using power-up level of High to minimize register" {  } { { "sld_mbpmg.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_mbpmg.vhd" 309 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1\|holdff data_in VCC " "Warning: Reduced register \"sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1\|holdff\" with stuck data_in port to stuck value VCC" {  } { { "sld_mbpmg.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_mbpmg.vhd" 309 -1 0 } }  } 0}