📄 fpga2pc.fit.eqn
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--A1L75Q is fifo_wr~reg0 at LC_X17_Y7_N8
--operation mode is normal
A1L75Q_lut_out = STATE.WRITE_1;
A1L75Q = DFFEAS(A1L75Q_lut_out, !GLOBAL(clkin), GLOBAL(rst), , , , , , );
--A1L32Q is fifo_data[0]~reg0 at LC_X17_Y6_N0
--operation mode is arithmetic
A1L32Q_lut_out = !A1L32Q;
A1L32Q = DFFEAS(A1L32Q_lut_out, !GLOBAL(clkin), VCC, , A1L05, VCC, !GLOBAL(rst), , );
--A1L12 is fifo_data[0]~93 at LC_X17_Y6_N0
--operation mode is arithmetic
A1L12_cout_0 = A1L32Q;
A1L12 = CARRY(A1L12_cout_0);
--A1L22 is fifo_data[0]~93COUT1_125 at LC_X17_Y6_N0
--operation mode is arithmetic
A1L22_cout_1 = A1L32Q;
A1L22 = CARRY(A1L22_cout_1);
--A1L72Q is fifo_data[1]~reg0 at LC_X17_Y6_N1
--operation mode is arithmetic
A1L72Q_lut_out = A1L72Q $ (A1L12);
A1L72Q = DFFEAS(A1L72Q_lut_out, !GLOBAL(clkin), VCC, , A1L05, VCC, !GLOBAL(rst), , );
--A1L52 is fifo_data[1]~97 at LC_X17_Y6_N1
--operation mode is arithmetic
A1L52_cout_0 = !A1L12 # !A1L72Q;
A1L52 = CARRY(A1L52_cout_0);
--A1L62 is fifo_data[1]~97COUT1_126 at LC_X17_Y6_N1
--operation mode is arithmetic
A1L62_cout_1 = !A1L22 # !A1L72Q;
A1L62 = CARRY(A1L62_cout_1);
--A1L13Q is fifo_data[2]~reg0 at LC_X17_Y6_N2
--operation mode is arithmetic
A1L13Q_lut_out = A1L13Q $ (!A1L52);
A1L13Q = DFFEAS(A1L13Q_lut_out, !GLOBAL(clkin), VCC, , A1L05, VCC, !GLOBAL(rst), , );
--A1L92 is fifo_data[2]~101 at LC_X17_Y6_N2
--operation mode is arithmetic
A1L92_cout_0 = A1L13Q & (!A1L52);
A1L92 = CARRY(A1L92_cout_0);
--A1L03 is fifo_data[2]~101COUT1_127 at LC_X17_Y6_N2
--operation mode is arithmetic
A1L03_cout_1 = A1L13Q & (!A1L62);
A1L03 = CARRY(A1L03_cout_1);
--A1L53Q is fifo_data[3]~reg0 at LC_X17_Y6_N3
--operation mode is arithmetic
A1L53Q_lut_out = A1L53Q $ A1L92;
A1L53Q = DFFEAS(A1L53Q_lut_out, !GLOBAL(clkin), VCC, , A1L05, VCC, !GLOBAL(rst), , );
--A1L33 is fifo_data[3]~105 at LC_X17_Y6_N3
--operation mode is arithmetic
A1L33_cout_0 = !A1L92 # !A1L53Q;
A1L33 = CARRY(A1L33_cout_0);
--A1L43 is fifo_data[3]~105COUT1 at LC_X17_Y6_N3
--operation mode is arithmetic
A1L43_cout_1 = !A1L03 # !A1L53Q;
A1L43 = CARRY(A1L43_cout_1);
--A1L04Q is fifo_data[4]~reg0 at LC_X17_Y6_N4
--operation mode is arithmetic
A1L04Q_lut_out = A1L04Q $ !A1L33;
A1L04Q = DFFEAS(A1L04Q_lut_out, !GLOBAL(clkin), VCC, , A1L05, VCC, !GLOBAL(rst), , );
--A1L73 is fifo_data[4]~109 at LC_X17_Y6_N4
--operation mode is arithmetic
A1L73 = A1L83;
--A1L44Q is fifo_data[5]~reg0 at LC_X17_Y6_N5
--operation mode is arithmetic
A1L44Q_carry_eqn = (!A1L73 & GND) # (A1L73 & VCC);
A1L44Q_lut_out = A1L44Q $ A1L44Q_carry_eqn;
A1L44Q = DFFEAS(A1L44Q_lut_out, !GLOBAL(clkin), VCC, , A1L05, VCC, !GLOBAL(rst), , );
--A1L24 is fifo_data[5]~113 at LC_X17_Y6_N5
--operation mode is arithmetic
A1L24_cout_0 = !A1L73 # !A1L44Q;
A1L24 = CARRY(A1L24_cout_0);
--A1L34 is fifo_data[5]~113COUT1_128 at LC_X17_Y6_N5
--operation mode is arithmetic
A1L34_cout_1 = !A1L73 # !A1L44Q;
A1L34 = CARRY(A1L34_cout_1);
--A1L84Q is fifo_data[6]~reg0 at LC_X17_Y6_N6
--operation mode is arithmetic
A1L84Q_carry_eqn = (!A1L73 & A1L24) # (A1L73 & A1L34);
A1L84Q_lut_out = A1L84Q $ (!A1L84Q_carry_eqn);
A1L84Q = DFFEAS(A1L84Q_lut_out, !GLOBAL(clkin), VCC, , A1L05, VCC, !GLOBAL(rst), , );
--A1L64 is fifo_data[6]~117 at LC_X17_Y6_N6
--operation mode is arithmetic
A1L64_cout_0 = A1L84Q & (!A1L24);
A1L64 = CARRY(A1L64_cout_0);
--A1L74 is fifo_data[6]~117COUT1_129 at LC_X17_Y6_N6
--operation mode is arithmetic
A1L74_cout_1 = A1L84Q & (!A1L34);
A1L74 = CARRY(A1L74_cout_1);
--A1L15Q is fifo_data[7]~reg0 at LC_X17_Y6_N7
--operation mode is normal
A1L15Q_carry_eqn = (!A1L73 & A1L64) # (A1L73 & A1L74);
A1L15Q_lut_out = A1L15Q $ (A1L15Q_carry_eqn);
A1L15Q = DFFEAS(A1L15Q_lut_out, !GLOBAL(clkin), VCC, , A1L05, VCC, !GLOBAL(rst), , );
--A1L9 is altera_internal_jtag~TDO at JTAG_X1_Y13_N1
A1L9 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1_hub_tdo);
--A1L01 is altera_internal_jtag~TMSUTAP at JTAG_X1_Y13_N1
A1L01 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1_hub_tdo);
--A1L8 is altera_internal_jtag~TCKUTAP at JTAG_X1_Y13_N1
A1L8 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1_hub_tdo);
--altera_internal_jtag is altera_internal_jtag at JTAG_X1_Y13_N1
altera_internal_jtag = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1_hub_tdo);
--STATE.WRITE_1 is STATE.WRITE_1 at LC_X17_Y6_N9
--operation mode is normal
STATE.WRITE_1_lut_out = STATE.WRITE_2 # !fifo_full & STATE.WRITE_1 # !STATE.IDLE;
STATE.WRITE_1 = DFFEAS(STATE.WRITE_1_lut_out, !GLOBAL(clkin), GLOBAL(rst), , , , , , );
--clkin is clkin at LC_X8_Y13_N5
--operation mode is normal
clkin_lut_out = !clkin;
clkin = DFFEAS(clkin_lut_out, clk, GLOBAL(rst), , , , , , );
--A1L05 is fifo_data[7]~8 at LC_X17_Y6_N8
--operation mode is normal
A1L05 = fifo_full & STATE.WRITE_1;
--STATE.WRITE_2 is STATE.WRITE_2 at LC_X17_Y6_N8
--operation mode is normal
STATE.WRITE_2 = DFFEAS(A1L05, !GLOBAL(clkin), GLOBAL(rst), , , , , , );
--C1_hub_tdo is sld_hub:sld_hub_inst|hub_tdo at LC_X31_Y11_N6
--operation mode is normal
C1_hub_tdo = AMPP_FUNCTION(!A1L8, C1L51, C1L31, C1L91, C1L71, !HB1_state[8], HB1L81);
--STATE.IDLE is STATE.IDLE at LC_X17_Y7_N2
--operation mode is normal
STATE.IDLE_lut_out = STATE.WRITE_1 # STATE.WRITE_2 # !STATE.IDLE;
STATE.IDLE = DFFEAS(STATE.IDLE_lut_out, !GLOBAL(clkin), GLOBAL(rst), , , , , , );
--FB1_Q[3] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] at LC_X31_Y12_N5
--operation mode is normal
FB1_Q[3] = AMPP_FUNCTION(A1L8, FB3_Q[0], FB2_Q[3], FB6_Q[3], !C1L2, C1L22);
--FB1_Q[5] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[5] at LC_X31_Y12_N2
--operation mode is normal
FB1_Q[5] = AMPP_FUNCTION(A1L8, FB3_Q[0], FB6_Q[5], FB2_Q[5], !C1L2, C1L22);
--C1_jtag_debug_mode_usr1 is sld_hub:sld_hub_inst|jtag_debug_mode_usr1 at LC_X32_Y11_N3
--operation mode is normal
C1_jtag_debug_mode_usr1 = AMPP_FUNCTION(A1L8, K5_dffs[1], K5_dffs[0], C1L43, C1L53, HB1_state[0], HB1_state[12]);
--FB1_Q[4] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] at LC_X31_Y12_N9
--operation mode is normal
FB1_Q[4] = AMPP_FUNCTION(A1L8, FB3_Q[0], FB6_Q[4], FB2_Q[4], !C1L2, C1L22);
--C1L21 is sld_hub:sld_hub_inst|hub_tdo~275 at LC_X32_Y11_N1
--operation mode is normal
C1L21 = AMPP_FUNCTION(FB1_Q[4], C1_jtag_debug_mode_usr1);
--B1_bypass_reg_out is sld_signaltap:auto_signaltap_0|bypass_reg_out at LC_X32_Y11_N1
--operation mode is normal
B1_bypass_reg_out = AMPP_FUNCTION(A1L8, altera_internal_jtag, !B1_reset_all, GND, C1L13);
--C1L31 is sld_hub:sld_hub_inst|hub_tdo~276 at LC_X31_Y11_N5
--operation mode is normal
C1L31 = AMPP_FUNCTION(FB1_Q[3], FB4_Q[0], FB1_Q[5], C1L21);
--FB5_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] at LC_X28_Y11_N2
--operation mode is normal
FB5_Q[0] = AMPP_FUNCTION(A1L8, altera_internal_jtag, VCC, C1L02);
--F2_WORD_SR[0] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] at LC_X36_Y11_N4
--operation mode is normal
F2_WORD_SR[0] = AMPP_FUNCTION(A1L8, F2L82, F2_word_counter[0], F2_WORD_SR[1], F2L72, !F1_clear_signal, HB1_state[4], C1L4);
--JB1_dffe1a[0] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated|dffe1a[0] at LC_X30_Y11_N3
--operation mode is normal
JB1_dffe1a[0] = AMPP_FUNCTION(A1L8, FB6_Q[1], FB6_Q[3], C1L92, FB6_Q[2], !C1L2, C1L6);
--C1L41 is sld_hub:sld_hub_inst|hub_tdo~277 at LC_X30_Y11_N4
--operation mode is normal
C1L41 = AMPP_FUNCTION(F2_WORD_SR[0], JB1_dffe1a[0]);
--C1_HUB_BYPASS_REG is sld_hub:sld_hub_inst|HUB_BYPASS_REG at LC_X30_Y11_N4
--operation mode is normal
C1_HUB_BYPASS_REG = AMPP_FUNCTION(A1L8, C1L01, VCC, GND);
--C1L51 is sld_hub:sld_hub_inst|hub_tdo~278 at LC_X31_Y11_N9
--operation mode is normal
C1L51 = AMPP_FUNCTION(C1L41, FB5_Q[0], C1_jtag_debug_mode_usr1);
--K1_dffs[0] is sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:info_data_shift_out|dffs[0] at LC_X30_Y12_N7
--operation mode is normal
K1_dffs[0] = AMPP_FUNCTION(A1L8, K1_dffs[1], HB1_state[4], H1_is_buffer_wrapped_once, B1L23, !B1_reset_all);
--C1L61 is sld_hub:sld_hub_inst|hub_tdo~279 at LC_X30_Y12_N9
--operation mode is normal
C1L61 = AMPP_FUNCTION(K1_dffs[0], FB1_Q[3], FB1_Q[4]);
--K3_dffs[0] is sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|lpm_shiftreg:trigger_config_deserialize|dffs[0] at LC_X30_Y12_N9
--operation mode is normal
K3_dffs[0] = AMPP_FUNCTION(A1L8, K3_dffs[1], !B1_reset_all, GND, G1_trigger_setup_ena);
--C1L71 is sld_hub:sld_hub_inst|hub_tdo~280 at LC_X31_Y11_N0
--operation mode is normal
C1L71 = AMPP_FUNCTION(C1_jtag_debug_mode_usr1, FB4_Q[0], C1L61);
--FB6_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[0] at LC_X29_Y11_N5
--operation mode is normal
FB6_Q[0] = AMPP_FUNCTION(A1L8, FB6_Q[1], HB1_state[4], G1L3, !C1L2, FB6L4);
--F1_WORD_SR[0] is sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[0] at LC_X35_Y11_N5
--operation mode is normal
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