fpga2pc.map.rpt

this is a sample about usb in transmission,it s default installation is D:RedLogicRCII_samples, and

; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_th92:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 1024         ; 14           ; 1024         ; 14           ; 14336 ; None ;
+--------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+


+------------------------------------------------------------+
; State Machine - |fpga2pc|STATE                             ;
+---------------+------------+---------------+---------------+
; Name          ; STATE.IDLE ; STATE.WRITE_2 ; STATE.WRITE_1 ;
+---------------+------------+---------------+---------------+
; STATE.IDLE    ; 0          ; 0             ; 0             ;
; STATE.WRITE_2 ; 1          ; 1             ; 0             ;
; STATE.WRITE_1 ; 1          ; 0             ; 1             ;
+---------------+------------+---------------+---------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 307   ;
; Number of registers using Synchronous Clear  ; 21    ;
; Number of registers using Synchronous Load   ; 8     ;
; Number of registers using Asynchronous Clear ; 223   ;
; Number of registers using Asynchronous Load  ; 8     ;
; Number of registers using Clock Enable       ; 170   ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; fifo_wr~reg0                           ; 2       ;
; clkin                                  ; 131     ;
; sld_hub:sld_hub_inst|hub_tdo           ; 1       ;
; Total number of inverted registers = 3 ;         ;
+----------------------------------------+---------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                         ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                               ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------------------------+
; 3:1                ; 7 bits    ; 14 LEs        ; 7 LEs                ; 7 LEs                  ; Yes        ; |fpga2pc|sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[6]                        ;
; 18:1               ; 4 bits    ; 48 LEs        ; 32 LEs               ; 16 LEs                 ; Yes        ; |fpga2pc|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0]         ;
; 10:1               ; 4 bits    ; 24 LEs        ; 24 LEs               ; 0 LEs                  ; Yes        ; |fpga2pc|sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[3] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------------------------+


+-------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |fpga2pc ;
+----------------+-------+------------------------------------------------+
; Parameter Name ; Value ; Type                                           ;
+----------------+-------+------------------------------------------------+
; IDLE           ; 000   ; Binary                                         ;
; WRITE_1        ; 001   ; Binary                                         ;
; WRITE_2        ; 010   ; Binary                                         ;
+----------------+-------+------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------