cyclone_atoms.v

this is a sample about UART transmission,it s default installation is D:RedLogicRCII_samples, and th

                            qfbkin, 'b1);
            end
            	 
            // carry LUT
            icout0 = lut4(bin_mask, inverta_dataa, idatab, icin0, 'b0);
            icout1 = lut4(bin_mask, inverta_dataa, idatab, icin1, 'b0);
            	 
            if (icin_used == 1)
            begin
                if (icin0_used == 1 || icin1_used == 1)
                icout = (icin === 'b0) ? icout0 : icout1;
                else
                icout = lut4(bin_mask, inverta_dataa, idatab, 
                             icin, 'b0);
            end
            else  // inverta is used in place of cin
            begin
                if (icin0_used == 1 || icin1_used == 1)
                    icout = (iinverta === 'b0) ? icout0 : icout1; 
                else
                    icout = lut4(bin_mask, inverta_dataa, idatab, 
                                 iinverta, 'b0);
            end
        end
    end

    and (combout, data, 1'b1) ;
    and (cout, icout, 1'b1) ;
    and (cout0, icout0, 1'b1) ;
    and (cout1, icout1, 1'b1) ;
    and (regin, data, 1'b1) ;
   
endmodule

///////////////////////////////////////////////////////////////////////////////
//
//                              CYCLONE_LCELL_REGISTER
//
///////////////////////////////////////////////////////////////////////////////

`timescale 1 ps/1 ps
  
module cyclone_lcell_register (
                               clk, 
                               aclr, 
                               aload, 
                               sclr, 
                               sload, 
                               ena, 
                               datain,
                               datac, 
                               regcascin, 
                               devclrn, 
                               devpor, 
                               regout, 
                               qfbkout
                              );
input clk;
input ena;
input aclr;
input aload;
input sclr;
input sload;
input datain;
input datac;
input regcascin;
input devclrn;
input devpor ;

output regout;
output qfbkout;

parameter synch_mode = "off";
parameter register_cascade_mode = "off";
parameter power_up = "low";
parameter x_on_violation = "on";
   
reg iregout;
wire reset;
wire nosload;
   
reg regcascin_viol;
reg datain_viol, datac_viol;
reg sclr_viol, sload_viol;
reg ena_viol, clk_per_viol;
reg violation;
reg clk_last_value;
   
reg ipower_up;
reg icascade_mode;
reg isynch_mode;
reg ix_on_violation;

buf (clk_in, clk);
buf (iaclr, aclr);
buf (iaload, aload);
buf (isclr, sclr);
buf (isload, sload);
buf (iena, ena);
   
buf (idatac, datac);
buf (iregcascin, regcascin);
buf (idatain, datain);
   
    assign reset = devpor && devclrn && (!iaclr) && (iena);
    assign nosload = reset && (!sload);
   
    specify
        $setuphold (posedge clk &&& reset, regcascin, 0, 0, regcascin_viol) ;
        $setuphold (posedge clk &&& nosload, datain, 0, 0, datain_viol) ;
        $setuphold (posedge clk &&& reset, datac, 0, 0, datac_viol) ;
        $setuphold (posedge clk &&& reset, sclr, 0, 0, sclr_viol) ;
        $setuphold (posedge clk &&& reset, sload, 0, 0, sload_viol) ;
        $setuphold (posedge clk &&& reset, ena, 0, 0, ena_viol) ;
        
        (posedge clk => (regout +: iregout)) = 0 ;
        (posedge aclr => (regout +: 1'b0)) = (0, 0) ;
        (posedge aload => (regout +: iregout)) = (0, 0) ;
        (datac => regout) = (0, 0) ;
        (posedge clk => (qfbkout +: iregout)) = 0 ;
        (posedge aclr => (qfbkout +: 1'b0)) = (0, 0) ;
        (posedge aload => (qfbkout +: iregout)) = (0, 0) ;
        (datac => qfbkout) = (0, 0) ;
    
    endspecify
   
    initial
    begin
        violation = 0;
        clk_last_value = 'b0;
        if (power_up == "low")
        begin
            iregout <= 'b0;
            ipower_up = 0;
        end
        else if (power_up == "high")
        begin
            iregout <= 'b1;
            ipower_up = 1;
        end

        if (register_cascade_mode == "on")
            icascade_mode = 1;
        else
            icascade_mode = 0;

        if (synch_mode == "on" )
            isynch_mode = 1;
        else
            isynch_mode = 0;

        if (x_on_violation == "on")
            ix_on_violation = 1;
        else
            ix_on_violation = 0;
    end
   
    always @ (regcascin_viol or datain_viol or datac_viol or sclr_viol 
              or sload_viol or ena_viol or clk_per_viol)
    begin
        if (ix_on_violation == 1)
        violation = 1;
    end
   
    always @ (clk_in or idatac or iaclr or posedge iaload 
              or negedge devclrn or negedge devpor or posedge violation)
    begin
        if (violation == 1'b1)
        begin
            violation = 0;
            iregout <= 'bx;
        end
        else
        begin
            if (devpor == 'b0)
            begin
                if (ipower_up == 0) // "low"
                    iregout <= 'b0;
                else if (ipower_up == 1) // "high"
                    iregout <= 'b1;
            end
            else if (devclrn == 'b0)
                iregout <= 'b0;
            else if (iaclr === 'b1) 
                iregout <= 'b0 ;
            else if (iaload === 'b1) 
                iregout <= idatac;
            else if (iena === 'b1 && clk_in === 'b1 && 
                     clk_last_value === 'b0)
            begin
                if (isynch_mode == 1)
                begin
                    if (isclr === 'b1)
                        iregout <= 'b0 ;
                    else if (isload === 'b1)
                        iregout <= idatac;
                    else if (icascade_mode == 1)
                        iregout <= iregcascin;
                    else
                        iregout <= idatain;
                end
                else if (icascade_mode == 1)
                    iregout <= iregcascin;
                else 
                    iregout <= idatain;
            end
        end
        clk_last_value = clk_in;
    end
       
    and (regout, iregout, 1'b1);
    and (qfbkout, iregout, 1'b1);
   
endmodule

///////////////////////////////////////////////////////////////////////////////
//
//                                CYCLONE_LCELL
//
///////////////////////////////////////////////////////////////////////////////

`timescale 1 ps/1 ps

module cyclone_lcell (
                      clk, 
                      dataa, 
                      datab, 
                      datac, 
                      datad, 
                      aclr, 
                      aload, 
                      sclr,
                      sload,
                      ena,
                      cin,
                      cin0,
                      cin1,
                      inverta,
                      regcascin,
                      devclrn,
                      devpor,
                      combout,
                      regout,
                      cout, 
                      cout0,
                      cout1
                     );

input dataa;
input datab;
input datac;
input datad;
input clk; 
input aclr; 
input aload; 
input sclr; 
input sload; 
input ena; 
input cin;
input cin0;
input cin1;
input inverta;
input regcascin;
input devclrn;
input devpor ;

output combout;
output regout;
output cout;
output cout0;
output cout1;

parameter operation_mode = "normal" ;
parameter synch_mode = "off";
parameter register_cascade_mode = "off";
parameter sum_lutc_input = "datac";
parameter lut_mask = "ffff" ;
parameter power_up = "low";
parameter cin_used = "false";
parameter cin0_used = "false";
parameter cin1_used = "false";
parameter output_mode = "comb_only";
parameter lpm_type = "cyclone_lcell";
parameter x_on_violation = "on";
   
wire dffin, qfbkin;
   
cyclone_asynch_lcell lecomb (
                             .dataa(dataa),
                             .datab(datab), 
                             .datac(datac),
                             .datad(datad),
                             .cin(cin),
                             .cin0(cin0),
                             .cin1(cin1), 
                             .inverta(inverta),
                             .qfbkin(qfbkin),
                             .regin(dffin),
                             .combout(combout),
                             .cout(cout),
                             .cout0(cout0),
                             .cout1(cout1)
                            );
    defparam lecomb.operation_mode = operation_mode;
    defparam lecomb.sum_lutc_input = sum_lutc_input;
    defparam lecomb.cin_used = cin_used;
    defparam lecomb.cin0_used = cin0_used;
    defparam lecomb.cin1_used = cin1_used;
    defparam lecomb.lut_mask = lut_mask;
   
cyclone_lcell_register lereg (
                              .clk(clk),
                              .aclr(aclr),
                              .aload(aload),
                              .sclr(sclr),
                              .sload(sload),
                              .ena(ena), 
                              .datain(dffin), 
                              .datac(datac),
                              .regcascin(regcascin),
                              .devclrn(devclrn),
                              .devpor(devpor), 
                              .regout(regout),
                              .qfbkout(qfbkin)
                             );
    defparam lereg.synch_mode = synch_mode;
    defparam lereg.register_cascade_mode = register_cascade_mode;
    defparam lereg.power_up = power_up;
    defparam lereg.x_on_violation = x_on_violation;
   
endmodule



///////////////////////////////////////////////////////////////////////////////
//
//                            CYCLONE_RAM_REGISTER
//
///////////////////////////////////////////////////////////////////////////////

`timescale 1 ps/1 ps
  module cyclone_ram_register 
    (
     data, 
     clk, 
     aclr, 
     ena, 
     ifclk, 
     ifaclr, 
     ifena, 
     devclrn, 
     devpor, 
     powerup,
     dataout, 
     aclrout,
     clkout,
     done
     );
   
   parameter data_width = 144;
   parameter sclr = "true";
   parameter preset = "false";
   
   input [143:0] data;
   input 	 clk;
   input 	 aclr;
   input 	 ena;
   input 	 ifclk;